Design Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $150,400–$277,600 / yr
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $214k

$135k most similar roles pay here $293k

This role pays more than 69% of similar roles. Most pay $168,500–$227,900 — the shaded band above. At the midpoint, this role pays about $214k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

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The Design Verification Engineer joins the Hardware Technology organization to verify the functionality and performance of premier SOCs, IPs, or subsystems. Working within a vertical product model, you will collaborate with design, architecture, and software teams to review specifications and ensure quality through optimal testing. Your daily responsibilities include developing test plans, coverage plans, and next-generation verification methodologies while defining testbenches for complex components like Neural Engine hardware, DRAM subsystems, memory controllers, and high-speed IO standards such as PCI Express. You will utilize SystemVerilog, UVM, and digital simulation techniques to validate designs. Required skills include knowledge of computer architecture, data structures, algorithms, and scripting in Python or Perl. The role addresses critical challenges in chip design, including hardware security, power management, and media encoding systems for various codec formats.

What does a Design Verification Engineer earn in California?

Median $191200 from 59 postings across 7 companies.

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Skills

SystemVerilog UVM Digital Simulation Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Computer Architecture Digital Design Data Structures Algorithms

What you'll do

Verify the functionality and performance of premier System on Chip (SoC) designs.
Review design and architecture specifications to ensure high quality for SoCs, IPs, or subsystems.
Develop comprehensive test plans, coverage plans, and verification methodologies.
Build and maintain complex testbenches using SystemVerilog and UVM methodologies.
Define and implement next-generation verification methodologies for hardware components.
Identify corner conditions and use cases to drive specific test cases.
Execute digital simulation and debug processes to ensure design integrity.
Create scripts using Python or Perl to automate verification tasks.

What we're looking for

Bachelor of Science degree and at least 3 years of relevant industry experience.
Skilled in digital verification including constrained random, functional coverage, code coverage, and assertion methodology (preferred).
Knowledge of SystemVerilog, digital simulation, and debug (preferred).
Knowledge of computer architecture and digital design fundamentals (preferred).
Software programming skills with knowledge of data structures and algorithms (preferred).
Experience with Python, Perl, or similar scripting languages (preferred).
Knowledge of verification methodologies like UVM (preferred).
Experience with C/C++ or assembly (preferred).

10+ yrs exp

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