Design Verification Engineer

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Waltham, MA
Salary
$123,850–$175,200 / yr
Posted
1 day ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $150k
$111k most similar roles pay here $243k

This role pays less than 92% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $150k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Design Verification Engineer

As a Design Verification Engineer, you will join the hardware team to ensure the bug-free delivery of features through both functional and formal verification. You will develop detailed test and coverage plans based on microarchitecture while building scalable, portable verification environments including stimulus, checkers, assertions, trackers, and coverage components. Your daily responsibilities involve executing verification plans, performing design bring-up, enabling regressions for all features under your care, and debugging test failures at the block, IP, and SoC levels. You will utilize SystemVerilog, UVM, and scripting languages like Python, Perl, or Tcl to automate tasks. The role requires proficiency with EDA tools including Cadence Xcelium, VManager, Virtuoso, Jasper Gold, and Verdi. You will solve complex hardware problems by tracking progress through metrics such as bug reports and closing functional and code coverage gaps.

What does a Design Verification Engineer earn?

Median $195800 from 78 postings across 10 companies.

See salary data

What you'll do

  • Use functional and formal verification methods to ensure bug-free delivery of features.
  • Develop detailed test plans and coverage plans based on microarchitecture specifications.
  • Create scalable and portable verification methodologies for specific IP components.
  • Build comprehensive verification environments including stimulus, checkers, assertions, trackers, and coverage.
  • Execute design bring-up, regression testing, and debug test failures.
  • Develop block, IP, and SoC level test-benches using SystemVerilog and UVM.
  • Track and report progress using metrics such as bug counts and coverage reports.
  • Automate verification tasks using Python, Perl, or Tcl scripts.

What we're looking for

  • Master's degree or foreign equivalent in Computer Engineering or a related field.
  • Experience developing detailed test plans from design specifications.
  • Experience using SystemVerilog to verify high performance VLSI designs.
  • Experience using Universal Verification Methodology (UVM) to develop testbenches, tests, sequences, scoreboards, assertions, and coverage objects.
  • Experience setting up and executing regression suites.
  • Experience performing root-cause debugging of regression failures.
  • Experience analyzing functional and code coverage reports and closing coverage gaps.
  • Experience using Python, Perl, or Tcl to automate tasks.

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