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Active Keyword: CPU Physical Design Engineer Remove filter Clear all

7 of up to 20 (filtered)

CPU Server Physical Design Clock Engineer

Qualcomm

Austin, TX +1 2 days ago $148,300–$222,500
Actively hiring Posted this week Competitive pay
SPICE Python Kubernetes Terraform Docker CI/CD Prometheus Grafana PostgreSQL Git VLSI RTL Physical_Design Clock_Tree_Synthesis HDL Verilog SystemVerilog Cadence Synopsys Calibre
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Principal CPU Physical Design Engineer (San Diego, CA)

Qualcomm

San Diego, CA 8 days ago $211,900–$317,900
Actively hiring Verified listing Above market
TCL Python Synopsys Cadence RTL-to-GDSII ASIC SoC Physical Design Timing Closure Power Optimization EDA STA Signoff Place & Route Scripting Advanced Nodes PPA Trade-offs CPU Design Challenges Data-Driven Debugging
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Sr. Staff CPU Physical Design CAD Engineer

Qualcomm

Santa Clara, CA +1 41 days ago $198,700–$298,100
Actively hiring Above market
Tcl Python Cadence_Innovus Place-and-route Physical_Design Timing_Analysis Physical_Verification EDA Automation CI/CD
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CPU Physical Design Methodology and Optimization Engineer

Apple Inc

Santa Clara, CA 63 days ago $147,400–$272,100
Actively hiring Competitive pay
TCL Perl Python Synthesis PnR STA Physical_Design Digital_Circuits Timing Power_Concepts Logic_Design High_Performance_Physical_Design Low_Power_Physical_Design Deep_Sub_Micron_Technology
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CPU Server Physical Design Engineer

Qualcomm

Santa Clara, CA 64 days ago $167,100–$250,700
Actively hiring Competitive pay
C C++ Python Perl Verilog VHDL UVM SystemC Cadence Synopsys ModelSim Tensilica Instruction Extension (TIE) Linux
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