CPU Gate Level Synthesis Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $184,700–$324,800 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $255k

$129k $346k

below market most similar roles pay here above market

This role pays more than 95% of similar roles. Most pay $162,000–$229,100 — the blue band above. At the midpoint, this role pays about $255k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · CPU Gate Level Synthesis Engineer

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The CPU Gate Level Synthesis Engineer joins the Silicon Engineering Group to assess and optimize design quality for high-performance CPUs. This role involves driving early-stage development of low-power digital designs by running RTL to gate level synthesis and identifying opportunities to optimize timing, power, and area for micro-architectural features. Key responsibilities include performing early RTL health assessments, conducting power estimation, enhancing synthesis flows for post-route correlation, and integrating scan chain, ATPG, and MBIST with DFT teams. The engineer must also partner with timing teams for constraint generation and track PPA trends. Required skills include digital logic design, RTL synthesis, and physical design experience, with preferred proficiency in Tcl, Perl, and Python scripting for automation and flow optimization within the CPU implementation domain.

Skills

RTL Synthesis Digital Logic Design Physical Design Tcl Python Perl DFT ATPG MBIST Scan Chain Power Analysis RTL Optimization

What you'll do

Perform RTL to gate level synthesis to optimize timing, power, and area for micro-architectural features.
Conduct early RTL health assessments to identify and resolve potential timing and gate-depth issues.
Perform early-stage power estimation and validation for new micro-architectural features.
Enhance synthesis flows to ensure high correlation with post-route results for accurate feedback.
Integrate scan chain, ATPG, and MBIST into the synthesis flow in coordination with DFT teams.
Generate top-level constraints in partnership with the timing team.
Debug and resolve complex timing, power, and area issues to ensure scalable design performance.
Track and analyze PPA trends throughout the entire project cycle.

What we're looking for

Minimum BS degree in a relevant field.
Minimum 10+ years of relevant industry experience.
Experience in digital logic design, RTL synthesis, and physical design.
CPU implementation experience (preferred).
Proficiency in scripting languages such as Tcl, Perl, and Python (preferred).
Strong problem-solving, debugging, and collaboration skills in a fast-paced environment (preferred).

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