CPU Gate Level Synthesis Engineer

What you'll do

• Perform RTL to gate level synthesis to optimize timing, power, and area for micro-architectural features.
• Conduct early RTL health assessments to identify and resolve potential timing and gate-depth issues.
• Perform early-stage power estimation and validation for new micro-architectural features.
• Enhance synthesis flows to ensure high correlation with post-route results for accurate feedback.
• Integrate scan chain, ATPG, and MBIST into the synthesis flow in coordination with DFT teams.
• Generate top-level constraints in partnership with the timing team.
• Debug and resolve complex timing, power, and area issues to ensure scalable design performance.
• Track and analyze PPA trends throughout the entire project cycle.

What we're looking for

• Minimum of a Bachelor of Science degree is required.
• Experience in digital logic design, RTL synthesis, or physical design is required.
• CPU implementation experience is preferred.
• Proficiency in scripting languages such as TCL, Perl, and Python for automation and flow optimization is preferred.
• Strong problem-solving, debugging, and collaboration skills in a fast-paced environment are preferred.