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SoC Design RTL Verilog System Verilog UVM Python Perl Synthesis Physical Design Design Automation DFT CAD Scripting +8 more Show less

Synthesis Place and Route STA TCL Python Perl CSS HTML CGI Data Analytics CPU Design Automation +7 more Show less

Physical Design PnR STA Synthesis Python TCL Perl Machine Learning Digital Circuits Logic Design Deep Sub-micron Technology +6 more Show less

Physical Design STA Synthesis PnR TCL Python Perl Machine Learning Digital Circuits Logic Design Deep Sub-micron Technology +6 more Show less