This role pays more than
82%
of similar roles. Most pay
$174,600–$220,800
— the shaded band above.
At the midpoint, this role pays about
$240k
versus about
$198k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
The Connectivity Project Engineer, Principal joins the Data Center team to lead the planning and execution of high-performance, energy-efficient server solutions. This critical leadership role involves overseeing chipset development from concept through commercialization while ensuring key performance indicators regarding power, performance, area, and cost are met. The engineer will drive the resolution of technical issues across various functional blocks, identify project risks, and mitigate gaps in existing processes. Key responsibilities include collaborating with cross-functional teams to manage complex designs at advanced process nodes involving mixed-signal SerDes components, DDR, embedded processors, and IO chiplets. Required expertise includes semiconductor architecture, silicon characterization, and high-speed Ethernet or PCIe SerDes IP. The role focuses on solving technical challenges in the data center space by developing scalable, high-performance solutions for server products using advanced integrated circuit technologies.
Oversee chipset development to ensure key performance indicators for power, performance, area, schedule, and cost are met.
Drive the resolution of engineering issues across various functional blocks and components within the chipset.
Identify project risks and implement mitigation strategies to keep development on track.
Identify process gaps and influence the development of new methodologies to meet product specifications.
Report program status, progress, gaps, and risks to senior management.
Plan and execute projects through all phases from initial concept to final commercialization.
Perform engineering trade-off analyses for high-performance, low-power data center SoC designs.
What we're looking for
Bachelor's degree in Science, Engineering, or related field with 8+ years of experience, OR Master's with 7+ years, OR PhD with 6+ years of ASIC design/verification experience.
At least 15 years of experience in semiconductor product development including mixed-signal design, system design, SoC architecture, and hardware validation.
More than 10 years of experience in one or more areas of semiconductor product development.
More than 5 years of experience in a technical leadership role.
Expertise in architecting, designing, and validating high-performance solutions like SerDes, DDR, embedded processors, and power management.
Five or more years of experience in engineering trade-off analysis.
Experience developing high-speed Ethernet or PCIe SerDes IP or products (preferred).
Demonstrated track record in hyperscale data center solutions.
Palladium
RTL
Verilog
VHDL
Python
C
C++
SoC Architecture
Bluetooth
UWB
Pre-silicon Verification
Emulation
Digital Design
Firmware
FPGA
MAC
PHY
test-bench development