Connectivity Project Engineer, Principal

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$200,000–$300,000 / yr
Posted
40 days ago
Freshness
Confirmed live yesterday
Closes
Mar 16, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k
This role $250k
$104k $321k
below market most similar roles pay here above market

This role pays more than 90% of similar roles. Most pay $174,600–$214,500 — the blue band above. At the midpoint, this role pays about $250k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · Connectivity Project Engineer, Principal

The Connectivity Project Engineer, Principal joins the ASICS Engineering group within the Data Center team to lead the development of high-performance, energy-efficient server solutions. This role involves planning and executing projects from concept to commercialization, overseeing chipset development to ensure key performance indicators like PPA, schedule, and cost are met. You will drive the resolution of engineering issues across subsystems, identify project risks, and influence new development methodologies. Key responsibilities include architecting and validating complex designs at advanced process nodes, specifically focusing on mixed-signal SerDes, DDR, embedded processors, and IO chiplets. Required expertise includes semiconductor architecture, silicon characterization, and post-silicon validation. You will utilize skills in hardware design, SoC firmware development, and engineering trade-off analysis to solve complex problems for hyperscale data center solutions.

What you'll do

  • Oversee chipset development to ensure key performance indicators for power, performance, area, schedule, and cost are met.
  • Drive the resolution of engineering issues across various functional blocks and chipset components.
  • Identify project risks and implement mitigation strategies to keep development on track.
  • Identify process gaps and influence the development of new methodologies to meet product specifications.
  • Report periodically to senior management on program status, progress, gaps, and risks.
  • Provide supervision to direct and dotted-line reports while making significant organizational decisions.
  • Plan and execute projects through all phases from initial concept to commercialization.

What we're looking for

  • Bachelor's degree in Science, Engineering, or related field with 8+ years of ASIC design, verification, validation, or integration experience.
  • Master's degree in Science, Engineering, or related field with 7+ years of ASIC design, verification, validation, or integration experience.
  • PhD in Science, Engineering, or related field with 6+ years of ASIC design, verification, validation, or integration experience.
  • 15 years of experience in semiconductor product development including mixed-signal design, SoC architecture, and hardware validation.
  • More than 10 years of experience in one or more areas of semiconductor product development.
  • More than 5 years of experience in a technical leadership role.
  • More than 5 years of experience in engineering trade-off analysis.
  • Experience developing high-speed Ethernet or PCIe SerDes IP or SerDes-based Ethernet or PCIe products (preferred).

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