Chip Lead, Silicon Co-Design Group

Nvidia

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$196,000–$310,500 / yr
Posted
4 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $195k
This role $253k
$142k most similar roles pay here $329k

This role pays more than 88% of similar roles. Most pay $166,562–$223,700 — the shaded band above. At the midpoint, this role pays about $253k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Chip Lead, Silicon Co-Design Group

The Silicon Co-Design Group at NVIDIA is seeking a Chip Lead to serve as the technical lead for one of its critical silicon programs, ensuring the program’s technical integrity from early architecture through final product delivery. This role involves partnering across design, validation, software, and manufacturing teams to resolve complex multi-functional issues and guide feature integration. Day-to-day responsibilities include serving as the single point of contact for technical decisions, resolving challenging bugs related to HBM, power and thermal management, high-speed I/O, and packaging, and stewarding the qualification playbook. The ideal candidate has over a decade of experience in post-silicon bring-up, validation, or system integration at a major semiconductor company, with expertise in SoC and ASIC architecture and recognized contributions to silicon-level impact. Strong mentorship skills and the ability to build reusable technical methodologies are essential, as is comfort working across global teams and translating sophisticated issues into clear recommendations for executive leadership.

What you'll do

  • Serve as the single technical point of contact for multi-functional decisions and issues.
  • Co-lead program-level feature integration from chip to system, resolving inter-function dependencies.
  • Resolve complex multi-functional bugs by translating ambiguous symptoms into root-cause closure.
  • Steward the qualification playbook, guiding mitigations and capturing lessons for future use.
  • Shape the program’s technical narrative by surfacing key risks and trade-offs for leadership.
  • Lead Critical Debug and SCG Technical Execution forums, representing the chip externally.
  • Mentor Chip Leads on adjacent programs and contribute to SCG-wide methodology improvements.

What we're looking for

  • Over 12 years of experience in post-silicon bring-up, validation, or system integration at a major semiconductor company.
  • Proven track record leading technical decisions across functional boundaries without direct authority.
  • Strong understanding of SoC and ASIC architecture with recognized expertise in HBM, SerDes, power and thermal, or packaging.
  • Experience guiding multi-functional bug resolution and shaping the program’s technical narrative for executive leadership.
  • BS or MS (or equivalent experience) in Electrical or Computer Engineering plus a decade of relevant semiconductor industry experience.
  • History of building and sharing technical methodology beyond a single program, such as reusable playbooks or debug frameworks.
  • Comfort working through ambiguity with globally distributed teams and surfacing critical risks to leadership.

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