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ASIC Chip Lead

Broadcom

San Jose, CA +1 34 days ago
Actively hiring Confirmed live today High trust
Cadence Innovus TCL Python Calibre Formality LEC VCLP Physical Design Timing Closure Static and Dynamic IR drop Analysis Signal and Power EM checks Floorplanning Clock-tree implementation ESD Analog integration Synthesis STA RTL design
10+ yrs exp
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Principal Chip Lead, Silicon Co-Design Group

Nvidia

Santa Clara, CA 35 days ago $232,000–$368,000
Actively hiring Confirmed live today High trust Above market
ASIC Architecture Post-Silicon Bring-up Silicon Validation System Integration HBM SerDes Power and Thermal High-Speed I/O Packaging Co-Design Integration Debug Frameworks AI Tools
10+ yrs exp Hybrid
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Senior Chip Lead Engineer, SoC/ASIC

Amd

San Jose, CA 55 days ago $164,000–$246,000
Actively hiring Confirmed live today High trust Competitive pay
ASIC FPGA Verilog SystemVerilog VHDL RTL Design DFT Physical Design Timing Closure Power Optimization EDA Tools Silicon Validation Device Drivers System Software AI/ML Accelerators CPU GPU
10+ yrs exp
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Chip Lead / ASIC Director

Amd

San Jose, CA 152 days ago $248,800–$373,200
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design RTL Physical Design Post-silicon Validation FPGA Timing Closure Tapeout Verification Design for Test Architecture Electrical Engineering Computer Engineering
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