R&D Engineer IC Design 4

Broadcom

Quick summary

Work type: On-site
Location: Austin, TX
Salary: $108,000–$172,800 / yr
Posted: 16 days ago
Closes: Jul 14, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $184k

This role $140k

$95k most similar roles pay here $232k

This role pays less than 86% of similar roles. Most pay $155,275–$213,543 — the shaded band above. At the midpoint, this role pays about $140k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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At a glance

TL;DR · R&D Engineer IC Design 4

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As a senior front-end design engineer on the ASIC team, you will be responsible for defining architecture, designing logic blocks from system requirements, and conducting comprehensive verification through simulation and formal methods. Your daily tasks will involve synthesizing designs using tools like Synopsys Design Compiler or Cadence RTL compiler, analyzing timing with Primetime, and ensuring power efficiency at both RTL and gate level. You must also be proficient in scripting languages such as TCL/Perl, familiar with DFT methodologies, and adept at using version control systems like SVN and Git. This role requires a deep understanding of the entire ASIC design flow from synthesis to physical implementation, particularly for high-frequency designs at advanced technology nodes.

Skills

TCL Perl Synopsys Design Compiler Cadence RTL Compiler Primetime Liberty LIB models Synopsys Formality Cadence Conformal Spyglass Lint DFT svn git

What you'll do

Define architecture and design logic blocks based on system requirements.
Perform synthesis using Synopsys Design Compiler or Cadence RTL compiler.
Conduct timing analysis with Primetime for high-frequency designs.
Execute formal verification using tools like Synopsys Formality or Cadence Conformal.
Analyze power consumption at both RTL and gate level netlists.

What we're looking for

BS/MS in Electrical or Computer Engineering or equivalent
8+ years of ASIC design experience (or 6+ with MS)
Proficiency in TCL/Perl scripting and synthesis tools like Synopsys Design Compiler/Cadence RTL compiler
Expertise in timing analysis using Primetime for high-frequency designs
Formal verification skills with tools such as Synopsys Formality or Cadence Conformal
Experience with DFT methodologies and power analysis at both RTL and gate level
Familiarity with version control systems like SVN, Git

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