Cellular ASIC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $212,000–$386,300 / yr
Posted: 38 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $299k

$107k most similar roles pay here $416k

This role pays more than 99% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $299k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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As a Cellular ASIC Design Engineer at Apple's Hardware Technologies group, you will play a crucial role in developing high-performance, power-efficient cellular chips and SoCs. Your day-to-day responsibilities include establishing design guidelines for synthesis, place-and-route, timing closure, and signoff processes, optimizing EDA tool flows, and collaborating with various teams to enhance design productivity. You will also conduct detailed analysis of design databases and silicon validation data to optimize Power, Performance, Area, and Cost (PPAC) metrics using advanced tools like RedHawk, SeaHawk, Voltus, and Hspice. This role requires expertise in VLSI, RTL-to-GDSII flows, and experience with SoC power optimization and design technology co-optimization. Strong programming skills in Python, Perl, TCL, Unix shell, and C/C++ are essential for methodology automation. You will work on cutting-edge technologies like 3nm and beyond, driving innovation in the semiconductor industry.

Skills

Python Perl TCL Unix_shell C C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design_for_Test DFT ATPG Machine_Learning EDA_tools VLSI RTL_to_GDSII_flows

What you'll do

Develop and optimize design guidelines and EDA tool flows for advanced process technologies.
Identify and solve physical design bottlenecks to improve area efficiency and yield.
Conduct comprehensive analysis and validation of complex SoCs across various PVT corners.
Implement power optimization methodologies including voltage scaling and dynamic frequency scaling techniques.
Collaborate with multi-functional teams to enhance custom IP development and DFT strategies.
Apply ML modeling for predictive analysis and advanced design optimization.

What we're looking for

20+ years of VLSI industry experience with a focus on SoC design.
Expertise in Power, Performance, Area, and Cost optimizations for SoCs.
Hands-on experience with RTL to GDSII flows and advanced process technologies.
Proficiency in EDA tool development and optimization for synthesis, place-and-route, and signoff processes.
Experience in Design Technology Co-optimization and identifying scaling bottlenecks in new technology nodes.
Strong scripting skills and ability to rapidly prototype methodologies and test chip block implementations.

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