Cellular ASIC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $201,300–$367,400 / yr
Posted: 38 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $188k

This role $284k

$109k most similar roles pay here $395k

This role pays more than 99% of similar roles. Most pay $158,850–$216,250 — the shaded band above. At the midpoint, this role pays about $284k versus about $188k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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As a Cellular ASIC Design Engineer at Apple's Hardware Technologies group, you will play a critical role in developing high-performance, power-efficient cellular chips and system-on-chips (SoC) for next-generation devices. Your daily tasks will include establishing design guidelines and optimizing EDA tool flows to enhance Power, Performance, Area, and Cost efficiency metrics. You'll collaborate with various teams to ensure timing closure and develop innovative solutions for physical design challenges in advanced process technologies like 3nm and beyond. Additionally, you’ll perform detailed analysis using Spice simulations and power optimization tools, while also driving DFT methodology improvements and supporting the bring-up of new process technologies. This role requires expertise in VLSI with hands-on experience in RTL to GDSII flows, proficiency in scripting languages such as Python, Perl, TCL, Unix shell, and C/C++, and a strong understanding of design technology co-optimization.

Skills

Python Perl TCL Unix shell C C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design Technology Co-optimization Power Optimization ML modeling EDA tools

What you'll do

Develop and optimize design guidelines and EDA tool flows for advanced process technologies.
Identify and resolve physical design bottlenecks to improve area efficiency and yield.
Conduct comprehensive analysis and validation of complex SoCs using Spice simulations and timing signoff tools.
Implement power optimization methodologies including voltage scaling and dynamic frequency/voltage techniques.
Collaborate with multi-functional teams to enhance custom IP development and advanced process technology bring-up.

What we're looking for

At least 20 years of VLSI industry experience with a BS degree.
Expertise in Power, Performance, Area, and Cost optimizations for SoCs.
Hands-on experience with RTL to GDSII flows.
Experience in Design Technology Co-optimization and identifying scaling bottlenecks.
Proficiency in rapid prototyping and scripting methodologies.
Strong analytical skills and ability to apply data science and ML analytics.

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