Cellular ASIC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 38 days ago

Market check

Salary context

How this pay compares to similar roles

Similar $188k

$129k most similar roles pay here $230k

This listing doesn't post a salary. Most similar roles pay $158,850–$216,250.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 638 open roles on FindRole.

Listed pay typically runs $171,600–$272,100 across 505 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Cellular ASIC Design Engineer

Apply Now Log in to save

As a Cellular ASIC Design Engineer at Apple’s Hardware Technologies group, you will play a critical role in developing high-performance, power-efficient cellular chips and SoCs. Your day-to-day responsibilities include establishing design guidelines for synthesis, place-and-route, timing closure, and signoff processes, optimizing EDA tool flows, and driving improvements to enhance design productivity. You will also collaborate with physical design teams on timing closure and work closely with CAD, IP, and Design Technology teams to develop innovative solutions. Key skills required are expertise in Power, Performance, Area, and Cost optimizations for SoCs, experience with VLSI RTL-to-GDSII flows, and proficiency in Python, Perl, TCL, Unix shell, and C/C++ programming for methodology automation. This role demands a deep understanding of advanced process technologies like 3nm and beyond, as well as the ability to apply data science and ML analytics for continuous design optimization.

Skills

Python Perl TCL Unix shell C/C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design Technology Co-optimization ML modeling

What you'll do

Develop and optimize design guidelines and EDA tool flows for advanced process technologies.
Identify and resolve physical design bottlenecks to improve area efficiency and yield.
Conduct comprehensive analysis and validation of designs across various PVT corners.
Implement power optimization techniques including voltage scaling and dynamic frequency scaling.
Collaborate with multi-functional teams to enhance custom IP development and DFT methodologies.
Stay updated on industry trends and apply ML modeling for predictive design optimization.

What we're looking for

Extensive VLSI experience with hands-on expertise in RTL to GDSII flows.
Expertise in Power, Performance, Area, and Cost optimizations for SoCs.
Proficiency in SoC power flows and Vmin optimization techniques.
Experience identifying and solving scaling bottlenecks in new technology nodes.
Strong background in rapid prototyping and scripting methodologies.
Knowledge of physical design challenges and synthesis tools proficiency.
Application of data science and ML analytics to fine-tune implementation.

Similar roles

Cellular ASIC Design Engineer

Apple Inc

Sunnyvale, CA 38 days ago $212,000–$386,300

Python Perl TCL Unix_shell C C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design_for_Test DFT ATPG Machine_Learning EDA_tools VLSI RTL_to_GDSII_flows

Save

Cellular ASIC Design Engineer

Apple Inc

San Diego, CA 38 days ago $201,300–$367,400

Python Perl TCL Unix shell C C++ Hspice Finesim AFS Spectre Infinisim RedHawk SeaHawk Voltus ICC2 Fusion Innovus Aprisa PT PT-SI Tempus DC/DCT/DCG/Genus/Oasis Design Technology Co-optimization Power Optimization ML modeling EDA tools

Save

Senior ASIC Design Engineer

Nvidia

Santa Clara, CA 26 days ago $136,000–$218,500

Verilog System-Verilog Python Perl Tcl Makefiles CDC checks Formal equivalence RTL design Synthesis Timing analysis DFT ATE test development Post-si bringup Debugging Behavioral real number modeling Mixed signal design Custom designed IPs Agentic AI flows

Save

Careers

Qualcomm

Santa Clara, CA 86 days ago

Python Perl AMBA AHB APB AXI PCIe USB CoreSight AI/ML DFT FPGA CDC Clocking_architecture NoC

Save

ASIC Design Engineer

Broadcom

Irvine, CA 65 days ago $108,000–$172,800

EDA Synthesis Design_for_Test Floorplanning Place_and_Route Clock_Methodology Power_Planning_Analysis Timing_Closure Signal_Integrity Physical_Design_Checks

Save

ASIC Design Engineer

Nvidia

Santa Clara, CA 67 days ago $116,000–$189,750

Verilog Perl Python C C++ Kubernetes Terraform CI/CD Docker PostgreSQL Git Jenkins Prometheus Grafana

Save