Careers
Quick summary
- Work type
- On-site
- Location
- San Diego, CA
- Posted
- 48 days ago
- Closes
- Oct 16, 2026
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $159,228–$216,250.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 270 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 196 roles with salary data.
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At a glance
TL;DR · Careers
As a DTCO and Timing Engineer at Qualcomm Technologies, Inc., you will join the cutting-edge Design Technology Co-Optimization (DTCO) team to drive process technology entitlement analysis for SOC products in advanced node processes from 5nm down to 2nm. Your daily responsibilities include conducting Spice simulations using tools like Hspice and PrimeSim for power and performance validation, performing static timing analysis with PT/PT-SI and Tempus, and executing block-level PPA analysis through RTL-to-GDS flow utilizing FC Synthesis, Innovus, and other leading-edge EDA software. You will collaborate closely with foundry DTCO teams, CAD engineers, and IP developers to optimize Fmax, enhance PPAY, and reduce costs across multiple blocks. Essential skills include proficiency in Python, Perl, TCL, Unix shell scripting, and C/C++, along with strong programming abilities to support new process technology bring-ups from PDK to VLSI design.
Skills
What you'll do
- Conduct Spice simulations for power and performance validation using Hspice/Finesim/PrimeSim.
- Perform STA sign-off using PT/PT-SI and Tempus tools.
- Execute block level PPA analysis from RTL to GDS flow for hard macros.
- Collaborate with foundry DTCO team, EDA companies, CAD/IP teams on Fmax optimization.
- Improve design convergence process and support new advanced process technologies bring-up.
What we're looking for
- Experience in DTCO analysis for SOC products at block/IP-level and system-level.
- Proficient in Spice simulations and STA sign-off using industry-standard tools.
- Expertise in block level PPA analysis/implementation from RTL to GDS flow.
- Strong collaboration skills with foundry, EDA companies, CAD team, and IP team.
- Excellent programming skills in Python, Perl, TCL, Unix shell, and C/C++.
- Knowledge of advanced process technologies (5nm, 4nm, etc.) and PDK bring-up.
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