Careers
Quick summary
- Work type
- On-site
- Location
- Santa Clara, CA
- Posted
- 110 days ago
- Closes
- Aug 26, 2026
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $166,300–$225,650.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 753 open roles on FindRole.
Listed pay typically runs $152,950–$231,000 across 436 roles with salary data.
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At a glance
TL;DR · Careers
As a CPU Physical Design Timing Engineer at Qualcomm Technologies, Inc., you will join the NUVIA team to drive timing closure for Oryon CPU cores, collaborating closely with microarchitecture and RTL design teams to ensure aggressive power, area, and performance goals are met. Your day-to-day responsibilities include setting up STA constraints, conducting timing analysis across various conditions using tools like PT/Tempus, and developing automation scripts within STA/PD tools to enhance methodology. You will also work on cross-collaborative projects with Qualcomm’s central timing technology team and the CPU implementation team to optimize PPA goals. Essential skills for this role include expertise in STA timing analysis, AOCV/POCV concepts, CTS, and scripting languages such as TCL, Perl, Python, alongside familiarity with digital flow design tools like ICC2 and Innovus.
Skills
What you'll do
- Define and develop timing constraints for Oryon CPU Cores.
- Conduct timing analysis and validation across various PVT conditions using PT/Tempus.
- Optimize STA flow and correlate Spice to STA results.
- Debug root causes of timing miscorrelation at different design levels.
- Evaluate and implement new timing methodologies on diverse technology nodes.
- Develop automation scripts within STA/PD tools for methodology advancement.
What we're looking for
- Extensive experience in STA timing analysis and managing timing constraints.
- Proficiency in Prime-time and Tempus tools for STA flow optimization.
- Hands-on experience with digital design implementation from RTL to GDS using ICC2, Innovus.
- Strong scripting skills in TCL, Perl, and Python for automation and methodology development.
- Expertise in cross-talk noise, signal integrity, and layout parasitic extraction.
- Ability to drive timing convergence at chip-level and hard-macro level designs.
- In-depth knowledge of ASIC back-end design flows and methods.
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