Camera DV Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $148,300–$222,500 / yr
Posted: 18 days ago
Freshness: Confirmed live yesterday
Closes: Feb 20, 2027
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $189k

This role $185k

$139k most similar roles pay here $239k

This role pays less than 52% of similar roles. Most pay $152,825–$225,925 — the shaded band above. At the midpoint, this role pays about $185k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · Camera DV Engineer

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As a Camera DV Engineer within the Camera Engineering team, you will engage in technical discussions across design, software, and firmware teams to influence optimal imaging solutions and data flows. Your daily responsibilities include implementing test benches using object-oriented concepts and UVM methodology, writing parameterized verification plans, and creating complex constraints for algorithm and pipeline tuning scenarios. You will verify functionality against power and performance KPIs while utilizing simulation, formal, assertion, and emulation flows to achieve functional and code coverage. The role involves debugging issues across multiple platforms and designing AI-driven agentic workflows to enhance productivity. Required skills include expertise in SystemVerilog, OVM/UVM, and Verilog RTL traversal. This position focuses on the technical challenges of imaging systems within mobile, automotive, XR, IoT, and compute product spaces.

Skills

System Verilog UVM OVM Verilog RTL Hardware Verification Simulation Assertion Emulation Digital Design

What you'll do

Implement test benches using object-oriented concepts and UVM methodology to meet new requirements.
Write parameterized and scalable verification plans for imaging solutions.
Create complex constraints and sequences to simulate corner case algorithm and pipeline tuning scenarios.
Verify that functionality and Power/Performance KPIs are met across various platforms.
Utilize Simulation, Formal, Assertion, and Emulation flows to achieve functional and code coverage.
Debug complex issues across multiple verification platforms.
Write detailed technical documentation and feature descriptions for users and customers.
Design and implement AI-driven agentic workflows to improve verification productivity.

What we're looking for

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field and 4+ years of relevant experience.
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field and 3+ years of relevant experience.
PhD in Computer Engineering, Computer Science, Electrical Engineering, or a related field and 2+ years of relevant experience.
Experience with design verification including test plan definition, infrastructure development using OOP, and execution to meet metrics of closure.
Expertise with Hardware Verification Languages (HVL) such as SystemVerilog testbench (OVM/UVM).
Ability to develop directed and constrained random stimulus.
Strong digital design concepts and debugging skills with expertise in traversing Verilog/SystemVerilog RTL.
Ability to design and implement AI-driven agentic workflows to enhance verification productivity.

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