Camera DV Engineer

Qualcomm

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$155,400–$233,200 / yr
Posted
40 days ago
Freshness
Confirmed live today
Closes
Mar 16, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $194k
$139k $260k
below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $162,000–$239,550 — the blue band above. At the midpoint, this role pays about $194k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · Camera DV Engineer

The Camera DV Engineer joins the Camera Engineering team to support imaging solutions across Mobile, Automotive, XR, IoT, and Compute spaces. This role involves engaging in technical discussions with Design, Software, and Firmware teams to influence data flows and imaging solutions. Key responsibilities include implementing test benches using object-oriented concepts and UVM methodology, writing parameterized verification plans, and creating complex constraints for algorithm and pipeline tuning. The engineer will verify functionality against Power and Performance KPIs using Simulation, Formal, Assertion, and Emulation flows. Required skills include expertise in Hardware Verification Languages like SystemVerilog, developing directed and constrained random stimulus, and strong digital design debugging. The work focuses on human and computer vision technologies to solve complex imaging and verification productivity problems.

What you'll do

  • Implement test benches using object-oriented concepts and UVM methodology to meet new requirements.
  • Write parameterized and scalable verification plans for imaging solutions.
  • Develop complex constraints and sequences to create corner case algorithm and pipeline tuning scenarios.
  • Verify that functionality and Use-Case Power/Performance KPIs are met.
  • Use Simulation, Formal, Assertion, and Emulation flows to achieve functional and code coverage.
  • Debug complex issues across multiple verification platforms.
  • Write clear technical documentation and feature descriptions to guide users and customers.
  • Design and implement AI-driven agentic workflows to enhance verification productivity.

What we're looking for

  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of relevant work experience.
  • Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of relevant work experience.
  • PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of relevant work experience.
  • Experience with design verification defining test plans and developing verification infrastructure using OOP.
  • Expertise with Hardware verification languages (HVL) such as System Verilog testbench (OVM/UVM).
  • Experience developing Directed and Constrained Random stimulus.
  • Strong Digital Design concepts and debugging skills with expertise in traversing Verilog/System-Verilog RTL.
  • Ability to design and implement AI-driven agentic workflows to enhance verification productivity.

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