ASIC Verification - Team Lead | Microsoft Careers

Microsoft

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $142,800–$274,800 / yr
Posted: 9 days ago
Closes: Dec 2, 2026
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $200k

This role $209k

$127k most similar roles pay here $291k

This role pays more than 64% of similar roles. Most pay $177,250–$223,700 — the shaded band above. At the midpoint, this role pays about $209k versus about $200k for comparable roles.

Based on 240 similar postings.

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About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 1568 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 1397 roles with salary data.

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TL;DR · ASIC Verification - Team Lead | Microsoft Careers

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As a senior DPU Silicon Engineer on the Data Processing Unit team, you will play a pivotal role in developing high-performance ASICs designed to handle large data streams efficiently. Your day-to-day responsibilities include enhancing verification methodologies, defining test plans, and driving the development of comprehensive validation strategies for both pre-silicon and post-silicon phases. You will work closely with cross-functional teams to ensure that performance models meet stringent requirements and collaborate on architectural changes based on quantitative analysis. Key technologies and tools you’ll use include SystemVerilog, UVM, VCS, Simvision, Perl, C/C++, and Assembly, alongside AI-based verification acceleration tools. This role demands expertise in digital design, computer architecture (ARM, RISC-V, MIPS), AMBA protocols, and PCIe interfaces, as well as the ability to lead large-scale verification projects across geographic regions.

Skills

SystemVerilog UVM Perl C++ Assembly VCS Simvision Python AI_tools coverage_driven_verification functional_coverage code_coverage_analysis AMBA_protocols PCIe_interfaces digital_design computer_architecture ARM RISC_V MIPS CI/CD

What you'll do

Defines and implements verification strategies and test plans for complex SoC flows.
Develops performance models to identify bottlenecks and propose architectural changes.
Leads the creation of comprehensive post-silicon validation strategies and methodologies.
Drives development and implementation of silicon debug tools and capabilities.
Executes simulations using industry-standard tools and analyzes results to resolve issues.

What we're looking for

Experience with large-scale verification projects across multiple geographic regions.
Proficiency in UVM/SystemVerilog for testbench creation and maintenance.
Expertise in coverage-driven verification, functional coverage analysis.
Knowledge of digital design, computer architecture (ARM, RISC-V, MIPS).
Familiarity with AMBA protocols, Ethernet, and PCIe interfaces.
Strong collaboration skills to define verification scope and debug strategies.

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