ASIC DTCO, Timing and Technology Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$140,000–$210,000 / yr
Posted
4 days ago
Closes
Dec 21, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $175k
$130k most similar roles pay here $231k

This role pays less than 67% of similar roles. Most pay $164,600–$216,250 — the shaded band above. At the midpoint, this role pays about $175k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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At a glance

TL;DR · ASIC DTCO, Timing and Technology Engineer

As a DTCO and Timing Engineer at Qualcomm Technologies, Inc., you will join the cutting-edge Design Technology Co-Optimization (DTCO) team to drive advanced process technology entitlement for SOC products in mobile, compute, automotive, and IoT markets. Your daily responsibilities include conducting Spice simulations using Hspice/Finesim/PrimeSim/AFS/Spectre for power and performance validation, performing static timing analysis with PT/PT-SI and Tempus, and executing block-level PPA analysis from RTL to GDS flow using tools like FC Synthesis, Innovus, and Genus. You will collaborate closely with foundry DTCO teams, EDA companies, CAD engineers, and IP developers to optimize Fmax, enhance PPAY, and reduce costs for multiple blocks in advanced process nodes such as 5nm, 4nm, and beyond. Strong programming skills in Python, Perl, TCL, Unix shell, and C/C++ are essential, with additional value placed on machine learning modeling experience.

What you'll do

  • Conduct Spice simulations for power and performance validation using Hspice/Finesim/PrimeSim.
  • Perform STA sign-off using PT/PT-SI and Tempus tools.
  • Execute block level PPA analysis and implementation from RTL to GDS flow.
  • Collaborate with foundry DTCO team, EDA companies, CAD/IP teams for Fmax optimization.
  • Improve design convergence process and support new advanced process technologies bring-up.

What we're looking for

  • Experience in DTCO analysis for SOC products at block/IP-level and system-level.
  • Proficiency in Spice simulations and STA sign-off using PT/PT-SI and Tempus tools.
  • Expertise in block level PPA analysis and implementation from RTL to GDS flow.
  • Strong collaboration skills with foundry, EDA companies, CAD team, and IP team.
  • Good programming skills in Python, Perl, TCL, Unix shell, and C/C++.
  • Knowledge of advanced process technologies (5nm, 4nm, etc.) bring-up in production.

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