This role pays less than
85%
of similar roles. Most pay
$157,500–$214,000
— the shaded band above.
At the midpoint, this role pays about
$143k
versus about
$186k
for comparable roles.
Based on 240 similar postings.
Employer
About General Dynamics
General Dynamics is a global aerospace and defense company offering a broad portfolio of products and services in business aviation, ship construction, land combat vehicles, and information technology. It serves customers in the U.S. government, allied governments, and a diverse array of commercial markets.
General Dynamics currently has
1261 open roles
on FindRole.
Listed pay typically runs
$121,975–$150,000
across 1075 roles with salary data.
Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions will join the engineering team to lead, develop, and maintain UVM-based and non-UVM verification environments for complex FPGA designs. The role involves creating comprehensive verification plans, implementing constrained-random stimulus generators, and driving code and functional coverage to closure. Key responsibilities include building CI/CD pipelines using Jenkins or GitLab CI, performing assertion-based verification with SystemVerilog Assertions, and debugging design issues via waveform analysis in QuestaSim or Vivado. The candidate will utilize SystemVerilog, VHDL, Python, Tcl, and Bash while verifying cryptographic engines, protocol interfaces like AXI4, and clock domain crossing concepts. This position focuses on the technical challenge of verifying cryptographic hardware implementations such as AES, GCM, SHA, ECC, and RSA within a cross-domain solutions framework to ensure robust system-level integration.
Develop and maintain UVM-based and non-UVM verification environments for complex FPGA designs and cryptographic engines.
Create comprehensive verification plans including functional coverage models, goals, and closure criteria.
Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog and VHDL.
Drive code and functional coverage to closure by analyzing gaps and developing targeted stimulus.
Build and maintain automated CI/CD pipelines for regression runs and coverage tracking using Jenkins or GitLab.
Perform assertion-based verification (ABV) using SystemVerilog Assertions to capture protocol rules and design invariants.
Debug complex design issues using waveform analysis, assertion failures, and coverage-driven investigation.
Support formal verification activities including property checking and equivalence checking where applicable.
What we're looking for
Bachelor's degree in Electrical or Computer Engineering (or related field) with 5 years of experience, or a Master's degree with 3 years of experience.
U.S. citizenship and the ability to obtain and maintain a Department of Defense Secret security clearance.
Proficiency in SystemVerilog and VHDL for verification, including constrained-random stimulus, functional coverage, and assertions.
Hands-on experience with UVM (Universal Verification Methodology) architecture, component development, and sequence libraries.
Experience with industry-standard simulation tools such as QuestaSim or ModelSim.
Ability to develop verification plans, define coverage models, and perform waveform debugging and signal-level analysis.
Knowledge of AXI-Stream, AXI4, and other on-chip bus protocols, along with clock domain crossing (CDC) concepts.
Experience verifying cryptographic hardware implementations (preferred); proficiency in scripting languages like Python, Tcl, or Bash (preferred).