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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Next-Gen High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture
4+ yrs exp
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Senior Digital Design Engineer, High-Speed I/O and Photonics

Nvidia

Santa Clara, CA 141 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday High trust Competitive pay
Verilog System Verilog RTL UVM Static Timing Analysis Synthesis P&R SerDes Ethernet InfiniBand PCIe USB Firmware Digital Design
5+ yrs exp Hybrid
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