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FPGA VHDL Verilog Digital Signal Processing DSP ASIC C C++ MATLAB SystemC Ethernet PCIe SPI UART SDRAM DDR JESD Git Bitbucket JIRA Modems Electronic Warfare +17 more Show less

Artificial Intelligence Large Language Models LLMs Prompt Engineering Data Architecture Data Pipelines Business Intelligence Digital Transformation Cybersecurity Data Governance AI Agents Full Stack Development Data & Analytics Automation Process Optimization Digital Strategy +10 more Show less

Embedded Software ASIC RTOS Linux Firmware I2C I3C SPI UART USB JTAG Ethernet Python Perl ARM DSP RF 4G 5G NR WiMAX 802.11ad Formal Verification Threat Modeling +18 more Show less

RF Systems Engineering MATLAB Python C++ ADS Ansys HFSS ASIC RFIC DSP Phased Array LTE 5G-NR WiFi 802.11 BLE Fixed Point Modeling Vector Spectrum Analyzer Signal Generators Logic Analyzers +13 more Show less

Digital Signal Processing Algorithm Development Waveform Simulation Machine Learning Artificial Intelligence Statistical Signal Processing Multi-rate Signal Processing OFDM Spatial Beamforming Channel Estimation Equalization Detection & Estimation Theory Random Processes Analysis Fixed-point Computation Agile R&D +11 more Show less

Agile Jira Requirements Analysis Business Process Modeling User Stories Technical Writing UX) Design Release Management Workflow Analysis Application Development Software Solutions +6 more Show less

Verilog SystemVerilog UVM AXI4 AXI‑Stream JESD204(B Aurora PCIe Vivado Vitis Quartus Python Tcl Git Azure DevOps CI/CD HLS C++ Linux Windows DMA SERDES Static Timing Analysis FPGA RFSoC +20 more Show less