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Active Keyword: Digital System Design Remove filter Clear all

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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 8 days ago $145,600–$218,400
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen System Cache ASIC Digital Design Engineer

Qualcomm

San Diego, CA 28 days ago $121,800–$182,600
Actively hiring Confirmed live yesterday Trusted Below market
ASIC Design RTL Design SystemVerilog Verilog Computer Architecture Synopsys Synthesis Low Power Design Python C++ C Coverage-based Design Verification SoC Interconnects Memory Controllers micro architecture Debugging
2+ yrs exp
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Next-Gen High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 48 days ago $145,600–$218,400
Actively hiring Confirmed live today Low trust Competitive pay
Verilog SystemVerilog ASIC Design RTL Design Synopsys Synthesis Low Power Design Python C C++ Computer Architecture Coverage-based Design Verification SOC Interconnects Memory Controllers micro architecture
4+ yrs exp
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Quantum Systems Digital Design Engineer II

Microsoft

75 days ago $102,100–$202,200
Actively hiring Confirmed live yesterday High trust Below market
Verilog SystemVerilog UVM AXI4 AXI‑Stream JESD204(B Aurora PCIe Vivado Vitis Quartus Python Tcl Git Azure DevOps CI/CD HLS C++ Linux Windows DMA SERDES Static Timing Analysis FPGA RFSoC
2+ yrs exp Hybrid
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