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Verilog SystemVerilog C C++ RTL Design Microarchitecture Power Management Clock Domain Crossing DVFS Firmware Silicon Validation Lint CDC Analysis Digital Design Low-power Design +10 more Show less

RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Power Management Logic Design +9 more Show less

RTL Micro-architecture Physical Design Python Perl TCL STA SPICE CMOS PrimePower PowerArtist Logic Design Device Physics Auto Place and Route +9 more Show less

VLSI Design Circuit Analysis Logic Design Python CMOS CPU Architecture Power Modeling Power Management Micro-architecture +4 more Show less

RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Waveform Debugging Power Management Logic Design +10 more Show less

RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Simulation Emulation Power Management Logic Design +9 more Show less

RTL Micro-architecture Physical Design Python Perl TCL STA SPICE CMOS PrimePower PowerArtist Logic Design Device Physics Auto Place and Route +9 more Show less

System Verilog UVM Python Perl Assembly Verilog Formal Verification UPF FPGA Simulation Emulation Low Power Simulation Scripting Silicon Debug +9 more Show less

System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Simulation Emulation Power Management Clock Control RTL +9 more Show less