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RTL Synthesis place-and-route PPA Logic Design Scripting Physical Design +2 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits Logic Design floor-planning Timing Budgeting Power Analysis Microarchitecture +7 more Show less

STA SPICE TCL Python Perl PnR ATPG Data Analysis Silicon Correlation Pre-silicon Design Post-silicon Debug tapeout +7 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits floor-planning Physical Design Power Analysis Memory Macros Standard Cells Logic Design +8 more Show less

RTL Synthesis PnR STA TCL Perl Digital Circuits Logic Design floor-planning Timing Budgeting Power Analysis Microarchitecture +7 more Show less

RTL Synthesis PnR STA TCL Perl Logic Design Digital Circuits floor-planning Timing Budgeting Power Analysis Microarchitecture +7 more Show less

Physical Design STA Spice CMOS Perl TCL Layout SoC Formal Verification DFM Computer Architecture Circuit Design Physical Verification +8 more Show less