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Active Keyword: Design Verification Lead Remove filter Location: San Jose Remove filter Clear all

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ASIC Design Verification Technical Leader

Cisco

San Jose, CA 23 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago Trusted Above market
SystemVerilog UVM ASIC Verification Python Perl Hardware Emulation FPGA Cadence Palladium Siemens Veloce Synopsys ZeBu PCIe Ethernet CXL HBM DDR RTL Silicon Bring-up Post-Silicon Validation
10+ yrs exp
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ASIC Design Verification Engineer, Technical Leader

Cisco

San Jose, CA 39 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago High trust Above market
System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation
8+ yrs exp
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ASIC Design Verification Engineering Leader

Cisco

Remote (San Jose, CA) 39 days ago $214,100–$309,800
Actively hiring Confirmed live yesterday High trust Above market
SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4
10+ yrs exp Remote
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Design Verification Lead

Amd

San Jose, CA 52 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
UVM SystemVerilog Verilog Python Perl ASIC FPGA PCIe CXL Ethernet High-Speed Connectivity Object-Oriented Programming HLS Simulation Verification Automation Computer Architecture
10+ yrs exp Hybrid
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