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Active Keyword: ASIC Design Verification Engineer I Remove filter Location: San Jose Remove filter Clear all

5 of up to 20 (filtered)

ASIC Design Verification Engineer I

Cisco

San Jose, CA +2 6 days ago $107,800–$157,400
Actively hiring Confirmed live yesterday Posted this week High trust Below market
SystemVerilog UVM Python Perl ASIC Design Design Verification SoC Veloce HAPS Functional Coverage Simulation Emulation ASIC Bring-up
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Senior ASIC Design Verification Engineer

Cisco

San Jose, CA 11 days ago $167,700–$245,200
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP
7+ yrs exp
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ASIC Design Verification Engineer

Cisco

San Jose, CA 16 days ago $155,000–$222,600
Actively hiring Confirmed live 3 days ago Trusted Competitive pay
System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification
5+ yrs exp
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ASIC Design Verification Engineer

Cisco

San Jose, CA 18 days ago $155,000–$222,600
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
System Verilog UVM Python Perl ASIC Design Verification Gate Level Simulation Veloce Palladium Zebu HAPS VC Formal IEV P4 PCIe CXL Ethernet RDMA DDR TCP
5+ yrs exp
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ASIC Design Verification Engineer, Technical Leader

Cisco

San Jose, CA 31 days ago $186,900–$267,700
Actively hiring Confirmed live yesterday High trust Above market
System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR MMU Veloce HAPS Formal Verification Simulation Emulation
8+ yrs exp
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