ASIC Design Verification Engineer I

Cisco

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CARTP, NCCarlsbad, CA
Salary: $107,800–$157,400 / yr
Employment: Full-time
Posted: 6 days ago
Freshness: Confirmed live yesterday
Closes: Nov 20, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $133k

$94k $239k

below market most similar roles pay here above market

This role pays less than 94% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $133k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 288 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 225 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · ASIC Design Verification Engineer I

Role Posting Log in to save

The ASIC Design Verification Engineer I joins the Silicon One team to develop revolutionary data center solutions. Working within a global team of experts, you will collaborate with designers and hardware engineers to verify ASICs during simulation, emulation, and bring-up to ensure seamless integration and optimal performance. Your daily responsibilities include maintaining and enhancing existing verification environments, constructing test benches with scoreboards, agents, sequencers, and monitors, and writing test plans to drive module verification closure. You will ensure complete coverage by reviewing code and functional coverage. Required technical skills include SystemVerilog and UVM methodology, along with scripting in Perl and Python. You will apply these skills to verify complex blocks, clusters, and top-level SoC designs, potentially utilizing Veloce or HAPS tools.

Skills

SystemVerilog UVM Python Perl ASIC Design Design Verification SoC Veloce HAPS Functional Coverage Simulation Emulation ASIC Bring-up

What you'll do

Maintain and enhance existing design verification environments.
Construct test benches including scoreboards, agents, sequencers, and monitors for new blocks.
Write comprehensive test plans and develop specific test cases.
Debug regression failures and drive them to module verification closure.
Ensure complete verification coverage through code implementation and functional coverage reviews.
Verify ASICs in simulation, emulation, and during hardware bring-up.

What we're looking for

Must have a Bachelor's degree completed within the past 3 years or expected within the next 12 months.
Qualifying education and work experience must be in ASIC Design, Design Verification, or a related field.
Experience with SystemVerilog and UVM methodology is required.
Experience with scripting using Perl and/or Python is required.
Experience using UVM and SystemVerilog for ASIC verification and verifying complex blocks or clusters (preferred).
Experience with functional coverage and constrained random DV environments (preferred).
Experience in verifying complex blocks, clusters, and top level for SoC (preferred).
Experience with Veloce/HAPS (preferred).

Save