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Digital Signal Processing ASIC FPGA MATLAB Python C++ GNU Radio Massive MIMO Beamforming Link Budgets Modem Design LTE WiFi Git JIRA Confluence Bitbucket Bamboo +13 more Show less

DevOps Kubernetes Istio Python C# Java Scala Go Apache Kafka Spark HBase HDFS Flink Linux Distributed Systems Monitoring Alerting Bare Metal +13 more Show less

RFIC Layout Analog Layout mixed signal design Python Perl Shell Scripting Linux Revision Control Systems Circuit Design Advanced Node IC Layout tape out Density Fill +7 more Show less

RFIC Analog IC Mixed-Signal SiGe CMOS Spectre ADS HFSS Momentum Phase-Locked Loops Vector Modulators Oscillators Mixers Filters Power Amplifiers QPSK APSK QAM Spectrum Analyzers Network Analyzers +15 more Show less

ASIC UVM OVM VMM RTL Python Constrained Random Verification Pre-silicon Verification Post-silicon Validation Chip Bring-up Test Bench Development Object-Oriented Programming Digital Design +8 more Show less

Power Integrity CST HFSS ADS Python C++ PDN SERDES DDR4 LPDDR5 GPDDR6 ASIC FPGA EMI/EMC High-Speed Digital Design Transmission Line Theory +11 more Show less

Power Integrity SERDES PDN CST HFSS ADS Python C++ DDR4 LPDDR5 GPDDR6 ASIC FPGA EMI/EMC High-Speed Digital Design Transmission Line Theory +11 more Show less

ASIC Silicon Design Tape-out FPGA ATE Testing Firmware Jira Smartsheet Confluence Project Management Product Lifecycle +6 more Show less

Vulnerability Management Offensive Security Python Go Java AWS Azure GCP CI/CD DevSecOps Penetration Testing Purple Teaming SIEM SOAR NIST CSF PCI SOX NYDFS +13 more Show less

DFT Siemens Tessent ATPG Python Perl Tcl C++ Gate-level Simulation SDF ATE Teradyn Advantest IEEE 1500 IEEE 1149.1 BIST Scan Insertion Post-silicon Validation +12 more Show less

Verilog System Verilog ASIC SoC RTL Design Python AXI AHB HDL Simulators EDA Tools Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up +10 more Show less