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Principal IC Design Engineer

Broadcom

Broomfield, CO +1 3 days ago $129,400–$207,000
Actively hiring Confirmed live 2 days ago Posted this week High trust Below market
Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL
10+ yrs exp
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Senior Digital / Mixed-Signal IC Design or Verification Engineer

Broadcom

Mendota Heights, MN +1 4 days ago $109,700–$175,500
Actively hiring Confirmed live 2 days ago Posted this week High trust Below market
UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting
8+ yrs exp
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