Browse tech roles

SoC Architecture SystemVerilog Verilog VHDL AMBA Synthesis Formal Verification CDC DFT Timing Closure Git JIRA DRAM SERDES UART Design Validation +11 more Show less

Verilog RTL Python STA DRC LVS EM/IR Synthesis Physical Design Place and Route Logical Equivalency Memory Subsystem Design Gate Netlist Synthesis Automation Scripts +9 more Show less

LLM Orchestration RAG LangGraph Model Context Protocol (MCP) Python TCL Docker Kubernetes REST APIs Microservices Vector Databases System Verilog UVM EDA Tool S Cloud-native Sandboxing +11 more Show less

Mainframe z/OS Broadcom Software SYSVIEW OPS/MVS NetMaster Mainframe Application Tuner REXX COBOL HLASM JES CICS MQ Series DB2 IMS VSAM ACF2 TSS RACF z/VSE z/VM +16 more Show less

Mixed-Signal Verification UVM SystemVerilog Verilog VHDL SVA Static Timing Analysis Logic Synthesis Place and Route Formal Verification Python Perl TCL CMOS Bipolar EDA Tools +11 more Show less

Python C++ Perl Tcl Linux Shell Scripting Silicon Validation PFA EFA SRAM CMOS Digital Circuits Device Physics Data Acquisition Memory Architectures Register-files ROM +12 more Show less

SRAM Register-files ROM Circuit Design Signal Integrity DFT Python Post-layout Simulation +3 more Show less

Python Java Large Language Models (LLMs) Agentic AI Retrieval-Augmented Generation (RAG) Distributed Systems Microservices Event-Driven Architecture CI/CD DevSecOps Apache Iceberg Vector Databases FHIR HL7 Knowledge Graphs APIs Cloud-Native Machine Learning Generative AI +14 more Show less

Mainframe z/OS Broadcom Software SYSVIEW OPS/MVS NetMaster Mainframe Application Tuner REXX COBOL HLASM JES CICS MQ Series DB2 IMS VSAM ACF2 TSS RACF z/VSE z/VM +16 more Show less