Browse tech roles

SystemVerilog UVM C++ VCS Digital Design Computer Architecture Assertion-Based Verification Functional Coverage Random Stimulus GDB Debussy Object-Oriented Programming Processor Pipeline Verification ASIC Verification +9 more Show less

SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS +10 more Show less

SystemVerilog UVM C C++ ASIC Verification Assertion-Based Verification Python Perl VCS IES GDB Debussy Functional Coverage Object Oriented Programming Memory Management Unit Computer Architecture Semiformal Verification (SFV +12 more Show less

ASIC SystemVerilog Verilog UVM Python Perl VCS Verdi Xcelium RTL Pre-silicon Verification infrastructure, automation Simulation Debug Root-cause Analysis +10 more Show less

SystemVerilog C++ UVM ASIC Verification VCS GDB Debussy Assertion-Based Verification Functional Coverage Random Stimulus Object Oriented Programming SoC GPU Memory Coherence High Speed IO Protocols +10 more Show less