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Innovus Fusion Compiler Physical Design Static Timing Analysis TCL Python Perl floor planning Clock Tree Synthesis Routing ECO CMOS IR/IVD Analysis Power Gating Clock Gating Multi-voltage Domain DRC LVC +13 more Show less

DRC LVS Cadence Virtuoso Cadence Innovus Tcl Python Perl CMOS Layout PnR APR RDL Physical Verification tape out +8 more Show less

PnR ICC2 Innovus PrimeTime TCL Python Perl Unix EMIR Voltus Redhawk Calibre floor planning Timing Closure Scripting +10 more Show less

Physical Design RTL GDSII Floor-planning Place and Route STA Verilog Perl Tcl LVS DRC Synthesis Power Grid Extraction SoC Architecture +10 more Show less

Physical Design RTL GDSII Floor-planning Place and Route STA LVS DRC Verilog Perl Tcl Synthesis Power Grid EM SoC Architecture +10 more Show less