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Active Keyword: FE Engineer Remove filter Location: Beaverton Remove filter Clear all

6 of up to 20 (filtered)

FE Engineer

Apple Inc

Beaverton, OR 1 day ago
Actively hiring Confirmed live today Posted today High trust
System Verilog Verilog RTL Static Timing Analysis STA Synopsys Cadence VCS Incisive PrimeTime Digital Logic Design Synthesis Verification Test Bench Logic Design
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Beaverton, OR 43 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Out-of-Order Execution Branch Prediction Instruction Fetch Register Renaming Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
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CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Beaverton, OR 43 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Instruction Fetch Branch Prediction Out-of-Order Execution Register Renaming Waveform Debugging
10+ yrs exp
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FE RTL Infrastructure CAD Engineer

Apple Inc

Beaverton, OR 129 days ago
Actively hiring Confirmed live today Trusted
Python Perl Verilog SystemVerilog EDA Tools Perforce RTL Generative AI Configuration Management Lint Clock Domain Crossing Reset Domain Crossing
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FE RTL Infrastructure CAD Engineer

Apple Inc

Beaverton, OR 129 days ago
Actively hiring Confirmed live today Trusted
Python Perl Verilog SystemVerilog EDA Tools Perforce RTL Build Configuration Management Generative AI Lint Clock Domain Crossing Reset Domain Crossing
3+ yrs exp
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CPU Technology Feasibility Engineer

Apple Inc

Beaverton, OR 139 days ago
Actively hiring Confirmed live today Low trust
RTL-to-GDS Synthesis place-and-route PnR PPA Optimization CPU Microarchitecture Clock Flow Physical Design Memory Design
10+ yrs exp
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