FE RTL Infrastructure CAD Engineer

As a FE RTL Infrastructure - CAD Engineer within the Silicon Technologies group, you will develop and support reliable infrastructure and work environments used by design and verification teams to modify, analyze, and verify RTL. Your daily responsibilities include managing RTL gatekeeping infrastructure for design collateral, developing soft IP release methodologies, and performing Perforce administration to ensure version control integrity. You will maintain a centralized configuration management system for various design views and drive innovation by building generative AI solutions to accelerate engineering productivity and improve reliability. The role also involves managing internal training materials and coordinating vendor sessions. To succeed, you must possess expertise in Python or Perl, along with knowledge of Verilog and SystemVerilog. You may also utilize front-end EDA tools for clock domain crossing, reset domain crossing, and linting processes.