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RTL Design Engineer, Power Design

Amd

Austin, TX 9 days ago $200,000–$300,000
Actively hiring Confirmed live yesterday High trust Above market
Verilog SystemVerilog Python Tcl Perl Ruby Makefile AMBA AXI AHB ASIC Design RTL Simulation Linting Synthesis Power-aware Verification Low-power Design SoC Microarchitecture
Hybrid

RTL Design Engineer

Apple Inc

Austin, TX 15 days ago
Actively hiring Confirmed live yesterday High trust
Verilog SystemVerilog RTL Design DSP Digital Logic Formal Verification Synthesis Static Timing Analysis DFT Python Perl GenAI Hardware-Software Co-design Low-power Design Pipelining Parallelization Testbenches Assertions
10+ yrs exp

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm

Santa Clara, CA +1 15 days ago $175,600–$263,400
Actively hiring Confirmed live yesterday Trusted Above market
RISC-V RTL Design Verilog VHDL Microarchitecture Python Perl Logic Design Functional Verification Waveform Debugging Instruction Fetch and Decode Branch Prediction Out-of-Order Execution
4+ yrs exp

RTL Design Engineer, Memory Controller

Arm Holdings

Austin, TX 16 days ago $198,100–$268,000
Actively hiring Confirmed live yesterday High trust Above market
SystemVerilog RTL Design Verilog VHDL AMBA LPDDR5 DDR5 HBM3 SoC Memory Controller Synthesis Lint CDC PPA Micro-architecture Logic Design
5+ yrs exp Hybrid

CPU Core RTL Design Engineer

Amd

Austin, TX 85 days ago $178,400–$267,600
Actively hiring Confirmed live yesterday High trust Above market
Verilog SystemVerilog RTL Design CPU Architecture ASIC SoC Logic Design Synthesis Timing Closure Python Tcl DFT Power Management Post-silicon Debug Place-and-Route
Hybrid