Wireless PHY Design Verification Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
12 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $206k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $170,637–$241,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $206k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · Wireless PHY Design Verification Engineer

Role Posting Log in to save

As a Wireless PHY Design Verification Engineer, you will join the Wireless Connectivity team to ensure first-time-right silicon success for sophisticated WiFi SoCs. You will be responsible for verifying complex WiFi PHY digital systems, including time and frequency-domain processing, hardware acceleration, calibration engines, and protocol implementations. Your daily work involves owning subsystem verification from test planning through coverage closure by building UVM environments, bus functional models, assertions, and infrastructure using DPIs to integrate algorithm models. You will architect constrained random scenarios for high-rate, low-power, and multi-link wireless features while applying data-driven methodologies like coverage tracking and gap identification. The role requires expertise in SystemVerilog, UVM, and ASIC verification flows to solve challenges in DSP subsystems and IEEE 802.11 protocols, ensuring robust performance across the product ecosystem through rigorous simulation and debugging.

Skills

UVM SystemVerilog ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Bus Functional Models Scoreboarding Transaction-Level Modeling

What you'll do

  • Develop UVM environments and bus functional models for DSP subsystems and IEEE 802.11 protocols.
  • Own subsystem verification from initial test planning through final feature closure.
  • Build testbench infrastructure, assertions, and DPIs to integrate algorithm models.
  • Architect and implement constrained random scenarios to exercise complex protocol interactions.
  • Execute data-driven verification closure using coverage tracking and gap identification metrics.
  • Drive verification strategies with cross-functional teams to achieve coverage across complex domains.

What we're looking for

  • Bachelor of Science degree and at least 10 years of relevant industry experience.
  • Track record of several tapeout cycles of sophisticated designs.
  • Experience verifying wireless, DSP, or digital communication systems.
  • Knowledge of ASIC verification flows with SystemVerilog and UVM including testbench architecture and coverage-driven methodologies.
  • Experience developing verification environments, bringing up complex designs, and debugging simulations.
  • Experience with constrained random testing, functional coverage implementation, and assertion-based verification.
  • Knowledge of IEEE 802.11 wireless protocols, Bluetooth, Cellular, or similar communication systems (preferred).
  • Experience with transaction-level modeling, System models via DPIs, and DSP algorithm verification strategies (preferred).

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