Wireless PHY Design Verification Engineer

Apple Inc

Confirmed live yesterday Low trust

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$122,700–$214,300 / yr
Posted
144 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $187k
This role $168k
$111k most similar roles pay here $232k

This role pays less than 63% of similar roles. Most pay $161,412–$212,718 — the shaded band above. At the midpoint, this role pays about $168k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Wireless PHY Design Verification Engineer

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As a Wireless PHY Design Verification Engineer, you will join the Wireless Connectivity team to ensure first-time-right silicon success for advanced WiFi SoCs. You will be responsible for verifying sophisticated WiFi PHY digital systems, including time and frequency-domain processing, hardware acceleration, calibration engines, and protocol implementations. Your daily work involves owning subsystem verification from test planning through coverage closure by building UVM environments, bus functional models, assertions, and infrastructure using DPIs to integrate algorithm models. You will architect constrained random scenarios for high-rate, low-power, and multi-link wireless features while applying data-driven methodologies like coverage tracking and gap identification. The role requires expertise in SystemVerilog, UVM, and ASIC verification flows to validate complex DSP subsystems and IEEE 802.11 protocols, ensuring robust performance across the product ecosystem through rigorous simulation and debugging of digital communication systems.

Skills

UVM SystemVerilog ASIC Verification IEEE 802.11 DSP Assertion-Based Verification Functional Coverage Scoreboarding Bus Functional Models Wireless Protocols Bluetooth Cellular Transaction-Level Modeling

What you'll do

  • Develop UVM environments and bus functional models for DSP subsystems and IEEE 802.11 protocols.
  • Own subsystem verification from initial test planning through final feature closure.
  • Build testbench infrastructure, assertions, and DPIs to integrate algorithm models.
  • Architect and implement constrained random scenarios to exercise complex protocol interactions.
  • Execute data-driven verification closure using coverage tracking and gap identification metrics.
  • Drive verification strategies with cross-functional teams to achieve coverage across complex domains.

What we're looking for

  • A bachelor's degree is required.
  • Candidates must have a track record of several tapeout cycles of sophisticated designs.
  • Experience verifying wireless, DSP, or digital communication systems is required.
  • Knowledge of ASIC verification flows using SystemVerilog and UVM is required.
  • Experience developing verification environments, bringing up complex designs, and debugging simulations is required.
  • Experience with constrained random testing, functional coverage implementation, and assertion-based verification is required.
  • Preferred knowledge includes IEEE 802.11 wireless protocols, Bluetooth, or Cellular systems.
  • Preferred experience includes transaction-level modeling, DSP algorithm verification, and integrating System models via DPIs.

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