Wireless PHY Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $120,300–$210,100 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $180k

This role $165k

$108k most similar roles pay here $232k

This role pays less than 58% of similar roles. Most pay $156,550–$202,500 — the shaded band above. At the midpoint, this role pays about $165k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless PHY Design Verification Engineer

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As a Wireless PHY Design Verification Engineer at Apple, you will join the Hardware team to ensure the success of multi-gigabit wireless technology by developing sophisticated UVM environments and bus functional models for complex DSP subsystems and IEEE 802.11 protocol verification. Your responsibilities include architecting verification strategies, creating constrained random scenarios, and applying data-driven methodologies to achieve coverage closure across high-rate, low-power, and low-latency features. You will work closely with cross-functional teams to bring up complex designs, develop testbench environments, and utilize algorithm models for DPI integration. The ideal candidate has experience in ASIC verification flows using SystemVerilog/UVM, as well as knowledge of wireless protocols like IEEE 802.11, Bluetooth, or Cellular systems.

Skills

SystemVerilog UVM IEEE 802.11 Bluetooth Cellular DPIs Transaction-Level Modeling Packet-Based Approaches Scoreboarding Assertions Constrained Random Testing Functional Coverage Implementation DSP Algorithms Verification Bit/Cycle Matching ASIC Verification Flows

What you'll do

Develop sophisticated UVM environments and bus functional models for complex WiFi PHY systems.
Own subsystem verification from test planning through coverage closure in high-rate wireless features.
Architect and implement constrained random scenarios to exercise complex protocol interactions.
Apply data-driven verification methodologies to track coverage, identify gaps, and measure metrics.
Collaborate with cross-functional teams to drive verification strategy across complex domains.

What we're looking for

Extensive experience in ASIC verification flows using SystemVerilog and UVM.
Track record of multiple tapeout cycles for complex designs.
Proficiency in developing sophisticated UVM environments and bus functional models.
Expertise in constrained random testing and assertion-based verification methodologies.
Knowledge of IEEE 802.11 wireless protocols or similar communication systems.
Experience with data-driven verification closure techniques, including coverage tracking.

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