Wireless PHY Design Verification Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Sunnyvale, CA
Salary: $126,800–$220,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $180k

This role $174k

$116k most similar roles pay here $232k

This role pays more than 60% of similar roles. Most pay $156,550–$202,500 — the shaded band above. At the midpoint, this role pays about $174k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Wireless PHY Design Verification Engineer

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As a Wireless PHY Design Verification Engineer at Apple, you will join the Hardware team to ensure the success of silicon designs through advanced verification methodologies. Your role involves developing sophisticated UVM environments and bus functional models for complex DSP subsystems and IEEE 802.11 protocol implementations, owning the verification process from test planning to coverage closure. You will architect constrained random scenarios, apply data-driven verification techniques, and collaborate with cross-functional teams to achieve comprehensive coverage across high-rate, low-power wireless features. Essential skills include experience in ASIC verification flows using SystemVerilog/UVM, knowledge of IEEE 802.11 protocols, and expertise in transaction-level modeling. This role demands a deep understanding of digital communication systems and the ability to drive verification strategies for cutting-edge wireless technologies.

Skills

SystemVerilog UVM IEEE 802.11 Bluetooth Cellular DPIs Transaction-Level Modeling Packet-Based Approaches Scoreboarding Assertions Constrained Random Testing Functional Coverage Implementation Coverage-Driven Methodologies DSP Algorithms Verification Bit/Cycle Matching

What you'll do

Develop sophisticated UVM environments and bus functional models for complex WiFi PHY systems.
Own subsystem verification from test planning through coverage closure in high-rate wireless features.
Architect and implement constrained random scenarios to exercise complex protocol interactions.
Apply data-driven verification methodologies, including coverage tracking and issue resolution.
Drive verification strategy with cross-functional teams to achieve comprehensive coverage across domains.

What we're looking for

Extensive experience in ASIC verification flows using SystemVerilog and UVM.
Track record of multiple tapeout cycles for complex designs.
Expertise in developing sophisticated UVM environments and bus functional models.
Proficiency in architecting constrained random scenarios and implementing functional coverage.
Knowledge of IEEE 802.11 wireless protocols and experience with verification methodologies.

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