below marketmost similar roles pay hereabove market
This role pays more than
95%
of similar roles. Most pay
$161,250–$250,375
— the blue band above.
At the midpoint, this role pays about
$325k
versus about
$206k
for comparable roles.
Based on 240 similar postings.
Employer
About HP Inc.
HP Inc. is a global technology company that develops and sells personal computers, printers, and related supplies and services. Its products include laptops, desktops, workstations, and printing solutions for consumers and businesses worldwide.
HP Inc. currently has
129 open roles
on FindRole.
Listed pay typically runs
$130,700–$205,200
across 103 roles with salary data.
The Vice President - PS Agentic AI PC Architecture & Development leads a global, matrixed engineering organization reporting to PS engineering leadership. This role is accountable for common Agentic AI systems architecture, engineering execution, and product delivery. The leader converts customer priorities into technical requirements and manages the integrated engineering plan from concept through production. Key responsibilities include owning device-aware AI execution, proximal intelligence, trusted agent execution, and agentic distribution. The role requires managing workload and memory governance, hardware-rooted trust, and distributed execution services. Candidates must possess expertise in systems engineering spanning hardware, firmware, silicon, memory, OS/runtime, and software. Core competencies include LLM inference, AI runtimes, agent frameworks, and managing trade-offs across performance, power, thermals, and security for client, server, and edge deployments.
Own the engineering delivery for Agentic AI systems from initial requirements through production release and sustaining.
Translate customer needs into functional requirements, engineering specifications, architecture, and prioritized development backlogs.
Own the common Agentic Computing Foundation architecture, including reusable libraries, services, and technical standards.
Manage device-aware AI execution, including workload governance, memory policies, and production orchestration.
Define technical roadmaps and integration contracts across OS, silicon, AI-runtime, and cross-platform technologies.
Lead technical engagements with OS, silicon, and AI model partners to align joint roadmaps and deliverables.
Build and lead a global engineering organization, managing hiring, performance, and engineering budgets.
Embed security, privacy, and reliability into the product lifecycle through architecture gates and test coverage.
What we're looking for
10+ years in systems engineering spanning hardware, firmware, silicon, memory, OS/runtime, and software with a record of shipping platform-level systems.
8+ years leading large, globally distributed, matrixed engineering organizations with shared or division-funded resources.
Demonstrated end-to-end delivery of complex products including requirements, architecture, development, integration, validation, production release, and sustaining.
Experience taking AI or Agentic AI systems from concept to production with measurable customer and revenue or margin impact.
Direct experience with server, data-center, or distributed/edge infrastructure including compute, memory, networking, and workload placement.
Experience building reusable platforms that scale across multiple product lines and deployment environments with sound judgment on system-level trade-offs.
Senior-level co-engineering experience with platform, silicon, and software partners to align division leaders and represent engineering at executive levels.
Working knowledge of identity, isolation, trust, and enterprise manageability, including Zero Trust, TPM/Secure Boot, and compliance requirements.
Practical experience with LLM inference, AI runtimes, agent frameworks, and coding in client and server environments (preferred).
Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field (preferred).
Agentic AI
On-device Inference
Systems Architecture
Windows
Linux
Firmware
GPU
NPU
CPU
Model Compression
Quantization
Hardware-in-the-loop
Interprocess Communication
Telemetry
Observability
Silicon SDKs
Performance Profiling