Standard Cell Design Methodology & Flow Engineer

What you'll do

• Act as the primary interface with internal CAD teams and foundries regarding production flows and PDK requirements.
• Coordinate with technology teams to integrate new process requirements into design tools and workflows.
• Implement sophisticated digital blocks using Verilog or SystemVerilog for simulation and formal verification.
• Apply data analysis and machine learning models to analyze timing, power, and area trends in large datasets.
• Automate standard cell development and integration flows using Python, TCL, or Perl to improve execution efficiency.
• Perform library characterization including timing, power, and noise modeling for complex macros and sequential flops.
• Execute various EDA tool tasks including synthesis, place-route, spice simulation, and DRC/LVS checks.

What we're looking for

• Bachelor of Science degree.
• Minimum of 10 years of relevant industry experience.
• Experience with Liberty formats, Spice simulation, and Static Timing and Power Analysis flows (preferred).
• Experience with timing modeling of large custom macros and complex sequential flops (preferred).
• Exposure to Design For Test, scan concepts, and writing DFT friendly RTL (preferred).
• Knowledge of FE modeling, Verilog/VHDL, and various EDA tools for characterization, synthesis, and verification (preferred).
• Data analysis and Machine Learning knowledge to study trends and perform QA on large datasets (preferred).
• Flow automation skills in standard cells development using Python, TCL, or Perl (preferred).