Standard Cell Design Methodology & Flow Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $172,100–$305,600 / yr
Posted: 62 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $239k

$128k most similar roles pay here $325k

This role pays more than 88% of similar roles. Most pay $165,200–$216,250 — the shaded band above. At the midpoint, this role pays about $239k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Standard Cell Design Methodology & Flow Engineer

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Join our world-class Digital Design Engineering team as a Standard Cell Design Methodology & Flow Engineer, where you will play a pivotal role in transforming innovative ideas into cutting-edge processor designs. In this senior-level position, you will collaborate closely with the custom digital circuits and library development teams to develop and refine production flows, interface with internal CAD teams and foundries, and implement sophisticated digital blocks using Verilog/SystemVerilog. You’ll also leverage data analysis techniques and machine learning models to study circuit trends and ensure quality in large datasets. This role requires expertise in library characterization, timing/power modeling, Spice simulation, static timing analysis, and flow automation, as well as proficiency with Python/TCL/Perl scripting languages and various EDA tools for design verification and validation.

Skills

Verilog SystemVerilog Python TCL Perl EDA tools Spice simulation Static Timing Analysis Power Analysis Machine Learning Data Analysis VHDL DRC/LVS RC Extraction Library Characterization Design For Test Formal Verification

What you'll do

Develop production flows by interfacing with internal CAD teams and foundries for PDK requirements.
Plan and implement new process requirements in collaboration with the technology team to enable necessary tools/flows.
Design sophisticated digital blocks using Verilog/SystemVerilog, conducting simulations or formal checks for verification.
Analyze circuit trends in timing, power, and area using data analysis techniques and machine learning models.
Automate standard cell development flows to enhance execution efficiency, utilizing Python/TCL/Perl scripts.

What we're looking for

At least 5+ years experience in standard cell library characterization and modeling.
Expertise in timing/power analysis flows, Liberty formats, and Spice simulation.
Experience implementing digital blocks in Verilog/SystemVerilog and conducting formal verification.
Proficiency in data analysis techniques and machine learning for quality assurance.
Skills in flow automation using Python/TCL/Perl for standard cell development.
Knowledge of FE modeling, VHDL, and various EDA tools for library characterization.
Understanding of device physics, process technology, and foundry ecosystem practices.

Hybrid

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