Standard Cell Design Methodology & Flow Engineer

What you'll do

• Act as the primary interface with internal CAD teams and foundries regarding production flows and PDK requirements.
• Coordinate with technology teams to integrate new process requirements into design tools and workflows.
• Implement sophisticated digital blocks using Verilog or SystemVerilog for simulation and formal verification.
• Apply data analysis and machine learning models to analyze timing, power, and area trends in large datasets.
• Automate standard cell development and integration flows using Python, TCL, or Perl to improve execution efficiency.
• Perform library characterization including timing, power, and noise modeling for complex macros and sequential flops.
• Execute physical verification tasks such as DRC/LVS and RC extraction for standard cell designs.

What we're looking for

• Bachelor of Science degree.
• Minimum of 10 years of relevant industry experience.
• Experience with Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, and Spice simulation (preferred).
• Experience with timing modeling of large custom macros and complex sequential flops (preferred).
• Exposure to Design For Test, scan concept, and writing DFT friendly RTL (preferred).
• Knowledge of implementation specification, design, timing, power, and flow automation (preferred).
• Data analysis and Machine Learning knowledge for studying data trends and performing QA on big datasets (preferred).
• Flow automation skills in standard cells development using Python, TCL, or Perl (preferred).