Standard Cell Design Methodology & Flow Engineer

What you'll do

• Define and plan production flows for internal CAD teams and coordinate PDK requirements with foundries.
• Develop new insights and integrate them into standard cell library designs, enhancing processor performance.
• Implement digital blocks in Verilog/SystemVerilog and conduct simulations or formal checks to ensure verification accuracy.
• Analyze circuit trends using data analysis techniques and machine learning models to identify quality issues early.
• Automate standard cell development flows to improve efficiency and streamline the integration process.

What we're looking for

• At least 10 years of relevant industry experience in digital design engineering.
• Extensive experience in standard cell library designs, including timing/power modeling.
• Proficiency in Verilog/SystemVerilog for implementing complex digital blocks.
• Expertise in data analysis and machine learning for quality assurance in large datasets.
• Strong skills in flow automation using Python/TCL/Perl for efficient execution.
• Knowledge of EDA tools for characterization, synthesis, place-route, and formal verification.
• Understanding of device physics and process technology in deep submicron technologies.