Cellular ASIC Design Engineer

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $175,000–$308,500 / yr
Posted: 149 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $196k

This role $242k

$131k most similar roles pay here $327k

This role pays more than 82% of similar roles. Most pay $168,000–$223,650 — the shaded band above. At the midpoint, this role pays about $242k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1984 open roles on FindRole.

Listed pay typically runs $175,000–$277,600 across 1590 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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As a Cellular ASIC Design Engineer within the Hardware Technologies group, you will design, optimize, and manufacture high-performance, power-efficient cellular chips and system-on-chips in advanced process technologies like 3nm and 2nm. You will develop methodologies for area efficiency, power optimization, and design technology co-optimization while managing synthesis, place-and-route, timing closure, and signoff processes. Your daily work involves building automation tools, performing Spice simulations for PVT corners, and implementing voltage scaling techniques like clock gating and dynamic frequency scaling. You will utilize EDA tools such as DC, ICC2, and Tempus, alongside programming languages including Python, Perl, TCL, and C/C++. Additionally, you will apply machine learning modeling for predictive analysis to solve complex scaling bottlenecks and improve design metrics across the RTL to GDS digital flow for advanced integrated circuits.

Skills

VLSI RTL to GDSII Synthesis Place and Route DFT Python TCL Perl C/C++ Unix Shell Hspice Finesim Spectre RedHawk SeaHawk Voltus SoC

What you'll do

Develop and optimize design methodologies for synthesis, place-and-route, timing closure, and signoff processes.
Create scripts and automation tools using Python, Perl, or TCL to improve design productivity.
Perform power optimization techniques including clock gating, power gating, and dynamic voltage scaling.
Conduct Spice simulations and STA correlation to validate PVT corners for advanced technology nodes.
Analyze design databases and silicon validation data to identify and resolve critical performance bottlenecks.
Execute Design Technology Co-optimization (DTCO) to improve PPA metrics in 3nm and 2nm processes.
Drive DFT methodology improvements including scan insertion, ATPG, and built-in self-test strategies.
Apply machine learning models for advanced design optimization and predictive analysis of hardware data.

What we're looking for

Minimum of a Bachelor's degree and 10 years of relevant industry experience.
VLSI background with hands-on experience in RTL to GDSII flows.
Experience optimizing Power, Performance, Area, and Cost for SoCs.
Experience with SoC power flows and Vmin optimization.
Expertise in Design Technology Co-optimization and identifying scaling bottlenecks in new technology nodes.
Ability to perform rapid prototyping and scripting of methodologies and test chip block implementation.
Proficiency in programming languages including Python, Perl, TCL, Unix shell, and C/C++.
Ability to apply data science and ML analytics for frontend, backend, and post-silicon data analysis.