Cellular ASIC Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $171,600–$302,200 / yr
Posted: 57 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $237k

$134k most similar roles pay here $320k

This role pays more than 82% of similar roles. Most pay $165,200–$223,700 — the shaded band above. At the midpoint, this role pays about $237k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Cellular ASIC Design Engineer

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The Technical Lead role within the Hardware team requires an experienced professional with a minimum of 10 years in relevant industry experience, ideally holding a BS degree. This senior-level position focuses on leading analysis and validation efforts for system-on-chip (SoC) designs, emphasizing power, performance, area, and cost optimizations. Day-to-day responsibilities include rapid prototyping methodologies, scripting test chip block implementations, and leveraging synthesis, place-and-route tools to explore implementation options. Candidates should possess a deep understanding of physical design challenges and be proficient in the latest EDA tools and scripting languages such as Python or Perl. This role is integral to addressing complex business problems related to high-scale semiconductor product development, ensuring efficient and optimized chip designs for cutting-edge technology solutions.

Skills

Power Performance Area Cost SoC Synthesis Place and Route Python Scripting Terraform CI/CD VLSI Physical Design Implementation Exploration

What you'll do

Lead power, performance, area, and cost optimizations for SoCs.
Develop and script rapid prototyping methodologies for test chip blocks.
Implement efficient design solutions to address physical design challenges.
Utilize synthesis, place and route tools for effective implementation exploration.
Guide technical direction and validate hardware designs through analysis.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
Experience in Power, Performance, Area, and Cost optimizations for SoCs.
Ability to rapidly prototype methodologies and implement test chip blocks.
Solid understanding of Physical Design challenges and proficiency with synthesis tools.
Expertise in place and route tools and implementation exploration.

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