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RTL-to-GDSII Physical Design STA DFT UPF Tcl Python Perl Shell Make Synthesis Floorplanning Clock Tree Synthesis Power Delivery Network Signoff SoC +11 more Show less

Physical Design Synthesis PnR STA CTS Floorplanning Routing UPF Python Tcl Innovus ICC2 Fusion Compiler Genus PrimeTime Tempus LEC VLSI +13 more Show less

Physical Design CAD Python Tcl Shell Synthesis place-and-route Static Timing Analysis Power Optimization Cadence Synopsys Calibre ICV DTCO PPA SoC GPU +12 more Show less