Senior Staff Engineer, RTL Memory Centric Computing

Samsung Semiconductor

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$189,000–$301,000 / yr
Posted
today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k
This role $245k
$146k most similar roles pay here $318k

This role pays more than 90% of similar roles. Most pay $177,800–$222,000 — the shaded band above. At the midpoint, this role pays about $245k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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At a glance

TL;DR · Senior Staff Engineer, RTL Memory Centric Computing

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Join our AGICL lab as a Senior Staff Engineer in RTL Memory Centric Computing, where you will develop and optimize IP for memory-centric computing systems using Verilog, SystemVerilog, and HLS, focusing on performance, power, and area efficiency. You’ll collaborate with verification engineers to design test plans, make informed design decisions across various constraints, troubleshoot hardware issues, and stay updated with advancements in machine learning and hardware architecture. Ideal candidates have a strong background in microarchitecture and computer architecture, at least 15 years of industry experience (or equivalent), and expertise in front-end RTL development for complex IPs, memory controllers, NOCs, interconnects, and AI/ML workloads.

Skills

Verilog System Verilog HLS Python CI/CD PostgreSQL Kubernetes AWS Terraform Docker Prometheus Grafana MLOps Git Jenkins

What you'll do

  • Develop IP for memory-centric computing systems using Verilog and System Verilog.
  • Optimize hardware designs for performance, power efficiency, and area constraints.
  • Collaborate with verification engineers to create comprehensive test plans.
  • Make informed design decisions considering trade-offs in performance, power, thermal, and cost.
  • Troubleshoot and debug hardware issues to ensure high-quality system delivery.

What we're looking for

  • 15+ years of industry experience with a Bachelor’s degree or equivalent
  • Strong background in microarchitecture and computer architecture
  • 5+ years of front-end design methodology involving RTL development for complex IPs
  • Experience designing Memory Controller, NOC, Interconnect IP, and Memory Centric computing IP
  • Expertise in AI/ML workloads and optimizing IP for performance, power, and area
  • Collaborative skills to develop test plans with Verification engineers and troubleshoot hardware issues
  • Up-to-date knowledge of machine learning and hardware architecture advancements

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