Sr. FPGA Engineer (Starshield)

SpaceX

Quick summary

Work type: On-site
Location: Hawthorne, CA
Salary: $160,000–$225,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $171k

This role $192k

$127k most similar roles pay here $236k

This role pays more than 62% of similar roles. Most pay $137,500–$205,000 — the shaded band above. At the midpoint, this role pays about $192k versus about $171k for comparable roles.

Based on 240 similar postings.

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About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 604 open roles on FindRole.

Listed pay typically runs $130,000–$155,000 across 440 roles with salary data.

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At a glance

TL;DR · Sr. FPGA Engineer (Starshield)

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As a Sr. FPGA Engineer on SpaceX’s satellite digital design team, you will work closely with other engineers to develop highly reliable FPGAs for safety-critical logic, sensors, cryptography, and RF/optical communications systems in the Starshield program. Your responsibilities include designing, implementing, and testing complex digital systems using RTL languages like Verilog or VHDL, integrating designs onto FPGA/SoC platforms, and collaborating with software and DSP engineers to validate software-defined radio systems. You will also bring up and validate devices that communicate to and fly in space, ensuring they meet stringent reliability standards. This role requires expertise in FPGA development across all stages, from RTL design to lab validation, as well as experience with Xilinx toolchains and high-rate conversion interfaces.

Skills

Verilog SystemVerilog VHDL FPGA SoC Xilinx RFSoC AD9361 DSP C C++ FFT FIR filter IIR filter RTL Python

What you'll do

Own and develop conceptual, architectural, and design components of digital systems for SpaceX satellites.
Implement logic designs and signal processing algorithms in RTL (Register Transfer Level) code.
Integrate FPGA/SoC platforms with high-throughput PS/PL interfaces.
Validate devices that communicate to or fly in space through rigorous testing processes.
Collaborate closely with RF/antenna, software, and DSP engineers on SDR system design.

What we're looking for

5+ years of professional software development experience or equivalent education
2+ years developing for FPGA platforms with Verilog, SystemVerilog, or VHDL
Experience in full lifecycle of FPGA development including RTL design and validation
Proficiency in integrating logic onto SoC platforms and designing high-throughput interfaces
Knowledge of DSP concepts such as spread spectrum, modulation schemes, and error correction

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