SoC DFT Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Cupertino, CA
Salary
$175,500–$311,700 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $210k
This role $244k
$138k most similar roles pay here $330k

This role pays more than 81% of similar roles. Most pay $177,250–$241,750 — the shaded band above. At the midpoint, this role pays about $244k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · SoC DFT Engineer

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As an SoC DFT Engineer within the Silicon Technologies group, you will be responsible for the complete design and manufacturing of high-performance, power-efficient system-on-chip processors. Your daily responsibilities include developing and implementing DFT architecture and infrastructure, generating structural test vectors to improve coverage, and collaborating with design verification teams to verify implementations and execute ECOs. You will work closely with designers on STA, physical, power, and logical issues while coordinating with test engineers to bring up test vectors on silicon. The role requires proficiency in Verilog or VHDL, experience with simulators and waveform debugging tools, and knowledge of industry standards such as ATPG, JTAG, and MBIST. You will also manage STA constraints for DFT modes and use scripting to analyze ATE data during the silicon debug phase.

Skills

DFT ATPG JTAG MBIST Verilog VHDL STA SDF Silicon Debug Design Verification Scripting Waveform Debugging ATE

What you'll do

  • Develop and implement DFT architecture for next-generation SoC designs.
  • Build and maintain the necessary DFT infrastructure for semiconductor design projects.
  • Verify DFT implementations in collaboration with the design verification team and implement ECOs.
  • Generate structural test vectors and analyze results to improve coverage.
  • Resolve STA, physical, power, and logical issues in coordination with designers.
  • Collaborate with test engineers to bring up test vectors on silicon.
  • Conduct experiments during silicon debug by gathering and analyzing ATE data using scripts.

What we're looking for

  • Bachelor of Science degree with at least 10 years of relevant industry experience.
  • Knowledge of industrial standards and practices in DFT, including ATPG, JTAG, MBIST, and trade-offs between test quality and time (preferred).
  • Experience developing DFT specifications and driving DFT architecture and methods for designs (preferred).
  • Knowledge of Verilog and/or VHDL, along with experience using simulators and waveform debugging tools (preferred).
  • Knowledge of industry standards for DFT and design tools (preferred).
  • Proven understanding of design verification methodologies for validating DFT implementation in simulation pre-silicon (preferred).
  • Experience debugging Compressed ATPG patterns, MBIST, and JTAG/1500 related issues (preferred).
  • Experience with STA constraints development and analysis for DFT modes and SDF simulations (preferred).

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