SoC Design and Integration Engineer

Qualcomm

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $164,000–$246,000 / yr
Posted: 6 days ago
Closes: Dec 19, 2026
Nearby: 99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $205k

$131k most similar roles pay here $258k

This role pays more than 63% of similar roles. Most pay $165,050–$216,250 — the shaded band above. At the midpoint, this role pays about $205k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 834 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 514 roles with salary data.

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View all roles at Qualcomm

At a glance

TL;DR · SoC Design and Integration Engineer

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Qualcomm Technologies seeks an experienced Senior ASIC Engineer to join its fast-paced SoC team responsible for high-performance ASICs in sub-5nm process nodes for mobile, AI, compute, and XR spaces. The ideal candidate will oversee the definition, design, verification, and documentation of ASIC development across various products, applying sound engineering practices with minimal supervision. Key responsibilities include determining architecture designs, logic design, system simulation, and developing tools for process automation. This role involves participating in IP design reviews, identifying flow improvements through automations, and providing feedback on silicon learnings to enhance design methodologies. Candidates should have a Master's degree in Electrical Engineering, Computer Science, or related fields with 5-10 years of experience in ASIC design, scripting, and architecture.

Skills

Verilog SystemVerilog VHDL Python Perl Shell TCL Cadence Synopsys Aldec Riviera-PRO ModelSim Xilinx Vivado ASIC design FPGA design RTL Design CI/CD Sub-5nm process nodes Mobile SoC AI SoC Compute SoC XR SoC

What you'll do

Define and oversee the architecture design for high-performance ASICs.
Develop RTL Design flows and methodologies for sub-5nm process nodes.
Resolve complex design and verification issues independently with minimal supervision.
Execute design and verification strategies in alignment with project specifications.
Participate in IP analyses, reviews, and feedback loops to enhance designs.
Identify and implement improvements through automation of design processes.

What we're looking for

Extensive experience (5-10 years) in ASIC design and FPGA development.
Strong background in RTL Design for high-performance ASICs at sub-5nm nodes.
Proficiency in developing tools and scripting for process automation.
Expertise in SoC architecture, logic design, integration, and system simulation.
Ability to resolve complex architectural and verification issues independently.
Experience in identifying and implementing flow and process improvements.
Excellent communication skills and teamwork for collaborative projects.

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