Signal Integrity Engineer

Broadcom

Quick summary

Work type
On-site
Location
San Jose Innovation Drive, CA
Salary
$141,300–$226,000 / yr
Posted
5 days ago
Closes
Nov 20, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $178k
This role $184k
$125k most similar roles pay here $237k

This role pays more than 65% of similar roles. Most pay $151,831–$205,000 — the shaded band above. At the midpoint, this role pays about $184k versus about $178k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 105 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 103 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Signal Integrity Engineer

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The ASIC Products Division at Broadcom is hiring a senior SI/PI engineer to join their team of experts developing cutting-edge IC solutions for AI/ML, cloud computing, wireless infrastructure, and networking. This role involves mask-based timing signoff using SPICE simulations, electromagnetic extraction, AC and transient analysis of PDNs, IO channel analysis, pre-layout modeling, and automating sign-off processes with EDA suppliers. The ideal candidate will have extensive experience in DDR/LPDDR or HBM SI/PI sign-off flows, proficiency in TCL and Python scripting for automation, and the ability to manage multiple projects under tight deadlines while working across a global organization. This position offers an exciting chance to innovate and contribute to the development of next-generation ASIC products using advanced 2.5D and 3D interconnect technologies.

Skills

SPICE Python TCL DDR LPDDR HBM SI/PI EDA Power Distribution Networks PCB Package Interposers Automate Documentation Presentations

What you'll do

  • Conduct mask-based timing signoff using time-domain simulations for parallel interfaces.
  • Perform electromagnetic extraction and modeling of signal and power delivery channels.
  • Execute AC and transient analysis on Power Distribution Networks.
  • Analyze IO channel performance to ensure optimal interface operation.
  • Develop pre-layout models for transceivers and signal networks.
  • Automate sign-off processes and collaborate with EDA suppliers for tool improvements.

What we're looking for

  • Extensive experience (10+ years) in electrical/electronics engineering or equivalent.
  • Proficiency in mask-based timing signoff using SPICE simulations for parallel interfaces.
  • Expertise in electromagnetic extraction and modeling of signal and power delivery channels.
  • Knowledge of DDR/LPDDR and HBM SI/PI sign-off flow tool suites.
  • Ability to manage multiple concurrent projects under tight deadlines.
  • Experience with various IC, package, and PCB database types.
  • Scripting skills in TCL or Python for automating routine tasks.

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