Senior Quantum Analog Layout Engineer

Microsoft

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $119,800–$234,700 / yr
Posted: 120 days ago
Freshness: Confirmed live yesterday
Closes: Nov 9, 2026
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $193k

This role $177k

$106k most similar roles pay here $248k

This role pays less than 52% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 598 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 586 roles with salary data.

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At a glance

TL;DR · Senior Quantum Analog Layout Engineer

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As a Senior Quantum Analog Layout Engineer on the Quantum 1st Party Hardware ASIC team, you will play a critical leadership role in advancing quantum analog infrastructure. You will be responsible for delivering Schematic-to-Graphic Database System layouts for high-performance, high-speed, and low-power IP designs across multiple process nodes, including deep FinFET. Your daily work involves developing plans for Analog Mask Layout execution, coordinating tasks for junior team members and external vendors, and establishing flow methodologies. You will utilize Cadence Virtuoso and other EDA tools to implement analog-intensive IPs such as VCOs, PLLs, and ADCs/DACs. The role focuses on the technical challenge of developing Application Specific Integrated Circuits (ASICs) and analog circuitry for quantum hardware, specifically addressing the requirements for designs that operate at cryogenic temperatures within a quantum computing framework.

Skills

Analog Layout Cadence Virtuoso EDA) tools FinFET ASIC SerDes floor-planning Signal Shielding

What you'll do

Deliver Schematic-to-Graphic Database System (GDS) layouts for high-performance, low-power IP designs across multiple process nodes.
Execute layout implementations of analog-intensive IPs using Cadence Virtuoso or equivalent design tools.
Develop execution plans and methodologies for Analog Mask Layout to deliver specific IP blocks.
Coordinate day-to-day tasks and project schedules for junior team members, contingent staff, and external vendors.
Establish and improve internal flows, processes, and methodologies for high-quality layout execution.
Manage the onboarding and offboarding of vendor partners and contingent staff to ensure quality and schedule targets.
Perform complex analog layout techniques including floor-planning, signal shielding, and thermal-aware designs.
Apply analog layout techniques specifically tailored for designs operating at cryogenic temperatures.

What we're looking for

A Doctorate in Physics or Engineering with 1+ year of experience, a Master's with 4+ years, or a Bachelor's with 6+ years is required.
Candidates must be able to pass Microsoft Cloud Background Checks and meet export control requirements (ITAR/EAR).
Candidates must provide proof of citizenship or protected status for access to export-controlled information.
Ability to use AI tools to drive innovation, performance modeling, and task automation in an "AI-first" environment is required.
Proficiency with Cadence Virtuoso and other EDA tools like Mentor or Synopsys is preferred.
Experience with high-performance analog blocks such as VCOs, PLLs, ADCs/DACs, and LDOs is preferred.
Knowledge of advanced layout techniques including common-centroid, matching, signal shielding, and thermal-aware designs is preferred.
Master's Degree in Physics, Engineering, or related field AND 4+ years.