Senior Quantum Analog Layout Engineer

Microsoft

Quick summary

Work type: On-site
Location: Redmond, WA
Salary: $119,800–$234,700 / yr
Posted: 45 days ago
Closes: Nov 9, 2026
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $193k

This role $177k

$106k most similar roles pay here $248k

This role pays more than 50% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 622 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 571 roles with salary data.

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At a glance

TL;DR · Senior Quantum Analog Layout Engineer

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As a Senior Quantum Analog Layout Engineer on Microsoft’s Quantum 1st Party Hardware ASIC team, you will lead the development of cutting-edge high-performance analog circuit layouts for quantum computing hardware, working across multiple process nodes including deep FinFET. Your responsibilities include executing schematic-to-GDS layouts, developing mask layout plans, and coordinating tasks with junior team members and external vendors to ensure timely delivery of high-quality designs. You will use Cadence Virtuoso and other EDA tools to implement analog-intensive IPs and establish methodologies for efficient execution. With 10+ years of experience in analog mask layout and IP delivery, you should be proficient in designing complex blocks like VCOs, ADCs/DACs, and LDOs, and have a deep understanding of cryogenic PDKs and thermal-aware layouts. This role offers the chance to contribute to transformative quantum technology at scale.

Skills

Cadence Virtuoso EDA tools Synopsys Mentor Graphics Schematic-Driven Layout (SDL) Voltage-Controlled Oscillators (VCOs) charge pumps interpolators bandgap references Phase-Locked Loops (PLLs) Analog-to-Digital Converters (ADCs) Digital-to-Analog Converters (DACs) Low-Dropout Regulators (LDOs) Serializer/Deserializers (SerDes) common-centroid layout matching symmetrical layouts signal shielding dummy devices thermal-aware layouts Electromigration/IR-drop (EM/IR)

What you'll do

Deliver GDS layouts for high-performance analog IPs across multiple process nodes using industry best practices.
Develop and execute mask layout plans for complex IP blocks, coordinating tasks with junior team members.
Implement analog-intensive IPs using Cadence Virtuoso tools, establishing design flows and methodologies.
Direct day-to-day execution of contingent staff and vendor partners to ensure quality and schedule adherence.
Support project planning, schedule tracking, and report generation for high-quality IP delivery.

What we're looking for

10+ years of experience in Analog Mask Layout execution and IP delivery.
Proficient use of Cadence Virtuoso and other EDA tools for schematic-driven layout.
Hands-on experience with high-performance analog blocks like VCOs, PLLs, ADC/DACs.
In-depth knowledge of analog design guidelines for high-speed and low-power designs.
Ability to coordinate tasks and deliverables with external vendors and contingent staff.
Demonstrated expertise in cryogenic Process Design Kits (PDKs) application.

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