Senior Mask Design Engineer - Hardware

Nvidia

Remote

Quick summary

Work type: Remote
Location: Santa Clara, CA
Salary: $132,000–$207,000 / yr
Posted: 53 days ago

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $180k

This role $170k

$123k most similar roles pay here $220k

This role pays less than 65% of similar roles. Most pay $155,425–$205,000 — the shaded band above. At the midpoint, this role pays about $170k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Mask Design Engineer - Hardware

Apply Now Log in to save

As a senior Mask Layout Design Engineer on our cutting-edge semiconductor team, you will be responsible for creating physical layouts for complex mixed-signal functions such as phase-locked loops (PLLs), high-speed serializers/deserializers (SerDes), analog-to-digital converters (ADCs), and ESD structures using advanced sub-micron CMOS technologies. Your daily tasks will involve leveraging Cadence tools to ensure the efficient and accurate design of these critical components, contributing to the development of innovative semiconductor products at scale. Ideal candidates possess a minimum of seven years of hands-on experience in mask layout design, along with expertise in physical design methodologies and an understanding of mixed-signal circuit behavior.

Skills

Cadence CMOS PLL SerDes Analog to Digital Converters ESD Structures Sub-micron Technology

What you'll do

Perform physical layout for mixed-signal functions such as PLLs and high-speed SerDes.
Design layouts for advanced sub-micron CMOS technologies using Cadence tools.
Create mask designs for analog to digital converters with precision.
Develop ESD structures within the framework of cutting-edge semiconductor processes.
Ensure compliance with design rules and standards in layout creation.

What we're looking for

At least 7 years of experience in mask and layout design for mixed-signal functions.
Expertise in physical layout for sub-micron CMOS technologies.
Proficient in using Cadence tools for layout design.
Experience with PLLs, high-speed SerDes, and analog to digital converters.
Knowledge of ESD structures designs in advanced semiconductor processes.