Senior Implementation Methodology Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
137 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $183k
This role $216k
$114k $281k
below market most similar roles pay here above market

This role pays more than 81% of similar roles. Most pay $151,168–$214,000 — the blue band above. At the midpoint, this role pays about $216k versus about $183k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Implementation Methodology Engineer

The Senior Implementation Methodology Engineer joins the elite VLSI team to own and improve the end-to-end RTL2GDS implementation methodology for advanced-node CPU builds. This role involves leading aggressive PPA optimization campaigns, evaluating new EDA tools, and developing next-generation efficiency automation to multiply engineering throughput. Key responsibilities include managing synthesis, place and route, CTS, and equivalence checking while serving as a technical liaison with vendors like Synopsys and Cadence. The candidate will build Python, TCL, and Perl automation frameworks to eliminate systemic bottlenecks and conduct rigorous A/B experiments to compare flow settings. Required expertise includes deep practical knowledge of the RTL2GDS flow, MCMM STA, and specific tools such as DC, ICC2, PrimeTime, Genus, and Innovus to solve complex timing closure and power issues.

What you'll do

  • Own and improve the end-to-end RTL2GDS implementation methodology for advanced-node CPU builds.
  • Lead aggressive PPA optimization campaigns throughout the full implementation cycle.
  • Evaluate new EDA tools and process node capabilities to provide clear adoption recommendations.
  • Serve as the technical liaison with EDA vendors to resolve tool issues and influence product roadmaps.
  • Build Python, TCL, and Perl automation frameworks to reduce manual engineering effort and improve turnaround time.
  • Conduct deep root-cause analysis on timing closure bottlenecks and power limiters to develop scalable solutions.
  • Execute rigorous A/B and multi-variant experiments to quantitatively compare flows and optimization strategies.
  • Define and enforce implementation methodology best practices and flow standards across development teams.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
  • 6+ years of hands-on proven experience in ASIC implementation methodology and EDA tool/flow development.
  • Deep, practical expertise in the complete RTL2GDS flow including synthesis, DFT, floorplanning, placement, CTS, routing, and MCMM STA.
  • Power user proficiency in synthesis and place-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus).
  • Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.
  • Demonstrated ability to drive complex, cross-functional technical initiatives and align build, CAD, and EDA vendor teams.
  • Prior experience in data-focused EDA tool evaluation, flow benchmarking, and methodology development with demonstrated PPA impact.
  • Demonstrated application of AI/ML or GenAI techniques to physical build, QoR analysis, flow automation, or design space exploration (preferred).

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