Senior Implementation Methodology Engineer

Nvidia

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Posted
91 days ago
Freshness
Confirmed live 2 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $178k
This role $216k
$103k most similar roles pay here $282k

This role pays more than 83% of similar roles. Most pay $149,642–$206,737 — the shaded band above. At the midpoint, this role pays about $216k versus about $178k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Implementation Methodology Engineer

The Senior Implementation Methodology Engineer joins the VLSI team to own and improve the end-to-end RTL2GDS implementation methodology for advanced-node CPU builds. This role involves managing synthesis, place and route, CTS, and equivalence checking while leading aggressive PPA optimization campaigns. The engineer will evaluate EDA tools from Synopsys and Cadence, serve as a technical liaison to vendors, and develop Python, TCL, and Perl automation frameworks to eliminate manual effort and improve design turnaround times. Key responsibilities include performing root-cause analysis on timing closure bottlenecks, conducting multi-variant experiments to compare flow settings, and implementing AI/ML-assisted flow optimizations. The role focuses on solving complex physical design challenges by creating scalable, data-driven methodologies that enhance engineering throughput and ensure high-quality silicon performance across the full implementation cycle for advanced processor designs.

What you'll do

  • Own and improve the end-to-end RTL2GDS implementation methodology for advanced-node CPU builds.
  • Evaluate new EDA tools and process node capabilities to provide adoption recommendations.
  • Serve as the technical liaison between internal teams and EDA vendors to resolve tool issues and influence roadmaps.
  • Conduct root-cause analysis on timing closure bottlenecks, power limiters, and long-tail quality of results (QoR) issues.
  • Develop Python, TCL, and Perl automation frameworks to reduce manual effort and improve design turnaround time.
  • Identify systemic efficiency bottlenecks and eliminate them through data-driven regression infrastructure and AI/ML-assisted optimization.
  • Partner with cross-functional teams to identify PPA opportunities and translate methodology improvements into measurable silicon impact.

What we're looking for

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 6+ years of hands-on experience in ASIC implementation methodology and EDA tool/flow development.
  • Deep expertise in the RTL2GDS flow including synthesis, DFT, floorplanning, placement, CTS, routing, and MCMM STA.
  • Proficiency as a power user of Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus) tools.
  • Experience in data-focused EDA tool evaluation, flow benchmarking, and methodology development with demonstrated PPA impact.
  • Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.
  • Ability to lead complex, cross-functional technical initiatives involving build, CAD, and EDA vendor teams.
  • Experience applying AI/ML or GenAI techniques to physical builds, QoR analysis, or flow automation is preferred.

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